PIC18F87K90-E/PT Microchip Technology, PIC18F87K90-E/PT Datasheet - Page 160
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PIC18F87K90-E/PT
Manufacturer Part Number
PIC18F87K90-E/PT
Description
128kB Flash, 4kB RAM, 1kB EE, 16MIPS, NanoWatt XLP, LCD, 5V 80 TQFP 12x12x1mm TR
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F66K90-IMR.pdf
(570 pages)
Specifications of PIC18F87K90-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Price
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Part Number:
PIC18F87K90-E/PT
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MICROCHIP
Quantity:
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Part Number:
PIC18F87K90-E/PT
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corresponding Data Direction and Output Latch registers
PIC18F87K90 FAMILY
11.3
PORTB is an 8-bit wide, bidirectional port. The
are TRISB and LATB. All pins on PORTB are digital only.
EXAMPLE 11-2:
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
DS39957D-page 160
CLRF
CLRF
MOVLW
MOVWF
PORTB, TRISB and
LATB Registers
PORTB
LATB
0CFh
TRISB
; Initialize PORTB by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
INITIALIZING PORTB
Four of the PORTB pins (RB<7:4>) have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur. Any RB<7:4>
pin configured as an output will be excluded from the
interrupt-on-change comparison.
Comparisons with the input pins (of RB<7:4>) are
made with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB<7:4> are ORed
together to generate the RB Port Change Interrupt with
Flag bit, RBIF (INTCON<0>).
This
power-managed modes. To clear the interrupt in the
Interrupt Service Routine (ISR):
a)
b)
c)
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared after one T
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
The RB<3:2> pins are multiplexed as CTMU edge
inputs. RB5 has an additional function for Timer3 and
Timer1. It can be configured for the Timer3 clock input
or Timer1 external clock gate input.
The RB<5:0> pins also are multiplexed with LCD seg-
ment drives that are controlled by bits in the registers,
LCDSE1 and LCDSE3. I/O port functionality is only
available when the LCD segments are disabled.
Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction). This will end
the mismatch condition.
Wait one instruction cycle (such as executing a
NOP instruction).
Clear flag bit, RBIF.
interrupt
2009-2011 Microchip Technology Inc.
can
wake
the
device
CY
delay.
from
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