PIC18F46K22-I/MV Microchip Technology, PIC18F46K22-I/MV Datasheet - Page 336

• Manufacturer Part Number: PIC18F46K22-I/MV
• Description: 64KB, Flash, 3968bytes-RAM,8-bit Family,nanoWatt XLP 40 UQFN 5x5x0.5mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46K22-I/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-UFQFN Exposed Pad
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Number Of Programmable I/os: 36
• Number Of Timers: 3 x 8-bit. 4 x 16-bit
• Operating Supply Voltage: 1.8 V to 5.5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18(L)F2X/4XK22
REGISTER 20-2:
TABLE 20-2:
DS41412D-page 336
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SRCON0
SRCON1
TRISA
TRISB
WPUB
Legend: Shaded bits are not used with this module.
SRSPE
Name
R/W-0
TRISA7
TRISB7
WPUB7
SRSPE: SR Latch Peripheral Set Enable bit
1 = SRI pin status sets SR Latch
0 = SRI pin status has no effect on SR Latch
SRSCKE: SR Latch Set Clock Enable bit
1 = Set input of SR latch is pulsed with DIVSRCLK
0 = Set input of SR latch is not pulsed with DIVSRCLK
SRSC2E: SR Latch C2 Set Enable bit
1 = C2 Comparator output sets SR Latch
0 = C2 Comparator output has no effect on SR Latch
SRSC1E: SR Latch C1 Set Enable bit
1 = C1 Comparator output sets SR Latch
0 = C1 Comparator output has no effect on SR Latch
SRRPE: SR Latch Peripheral Reset Enable bit
1 = SRI pin resets SR Latch
0 = SRI pin has no effect on SR Latch
SRRCKE: SR Latch Reset Clock Enable bit
1 = Reset input of SR latch is pulsed with DIVSRCLK
0 = Reset input of SR latch is not pulsed with DIVSRCLK
SRRC2E: SR Latch C2 Reset Enable bit
1 = C2 Comparator output resets SR Latch
0 = C2 Comparator output has no effect on SR Latch
SRRC1E: SR Latch C1 Reset Enable bit
1 = C1 Comparator output resets SR Latch
0 = C1 Comparator output has no effect on SR Latch
SRLEN
SRSPE
Bit 7
REGISTERS ASSOCIATED WITH THE SR LATCH
SRSCKE
R/W-0
SRCON1: SR LATCH CONTROL REGISTER 1
SRSCKE
WPUB6
TRISA6
TRISB6
Bit 6
W = Writable bit
‘1’ = Bit is set
SRSC2E
R/W-0
SRCLK<2:0>
SRSC2E SRSC1E
TRISA5
TRISB5
WPUB5
Bit 5
SRSC1E
R/W-0
WPUB4
Preliminary
TRISA4
TRISB4
Bit 4
U = Unimplemented
‘0’ = Bit is cleared
SRQEN
SRRPE
TRISA3
TRISB3
WPUB3
SRRPE
R/W-0
Bit 3
SRNQEN
SRRCKE
WPUB2
TRISA2
TRISB2
Bit 2
SRRCKE
R/W-0
SRRC2E
WPUB1
TRISA1
TRISB1
SRPS
Bit 1
 2010 Microchip Technology Inc.
C = Clearable only bit
x = Bit is unknown
SRRC2E
R/W-0
SRRC1E
TRISA0
TRISB0
WPUB0
SRPR
Bit 0
SRRC1E
R/W-0
on page
Values
Reset
335
336
154
154
155
bit 0