PIC16LF1906T-I/SS Microchip Technology, PIC16LF1906T-I/SS Datasheet - Page 157

• Manufacturer Part Number: PIC16LF1906T-I/SS
• Description: 14KB Flash, 512B RAM, LCD, 11x10b ADC, EUSART, NanoWatt XLP 28 SSOP .209in T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1906T-I/SS

• Processor Series: PIC16LF
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Data Ram Size: 512 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 1 x 16-bit, 1 x 8-bit
• Operating Supply Voltage: 1.8 V to 5.5 V
• Mounting Style: SMD/SMT
• Package / Case: QFN-28
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: LIN, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Eeprom Size: -
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Lead Free Status / Rohs Status: Details

18.1
The EUSART transmits and receives data using the
standard non-return-to-zero (NRZ) format. NRZ is
implemented with two levels: a V
represents a ‘1’ data bit, and a V
represents a ‘0’ data bit. NRZ refers to the fact that
consecutively transmitted data bits of the same value
stay at the output level of that bit without returning to a
neutral level between each bit transmission. An NRZ
transmission port idles in the mark state. Each character
transmission consists of one Start bit followed by eight
or nine data bits and is always terminated by one or
more Stop bits. The Start bit is always a space and the
Stop bits are always marks. The most common data
format is 8 bits. Each transmitted bit persists for a period
of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud
Rate Generator is used to derive standard baud rate
frequencies from the system oscillator. See
for examples of baud rate configurations.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent, but share the same data format and baud
rate. Parity is not supported by the hardware, but can
be implemented in software and stored as the ninth
data bit.
18.1.1
The EUSART transmitter block diagram is shown in
Figure
Transmit Shift Register (TSR), which is not directly
accessible by software. The TSR obtains its data from
the transmit buffer, which is the TXREG register.
18.1.1.1
The EUSART transmitter is enabled for asynchronous
operations by configuring the following three control
bits:
• TXEN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the TXEN bit of the TXSTA register enables the
transmitter circuitry of the EUSART. Clearing the SYNC
bit of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the EUSART. The programmer
must set the corresponding TRIS bit to configure the
TX/CK I/O pin as an output. If the TX/CK pin is shared
with an analog peripheral, the analog I/O function must
be disabled by clearing the corresponding ANSEL bit.
 2011 Microchip Technology Inc.
Note:
18-1. The heart of the transmitter is the serial
EUSART Asynchronous Mode
EUSART ASYNCHRONOUS
TRANSMITTER
The TXIF transmitter interrupt flag is set
when the TXEN enable bit is set.
Enabling the Transmitter
OL
OH
space state which
mark state which
Table 18-5
Preliminary
18.1.1.2
A transmission is initiated by writing a character to the
TXREG register. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TXREG is immediately
transferred to the TSR register. If the TSR still contains
all or part of a previous character, the new character
data is held in the TXREG until the Stop bit of the
previous character has been transmitted. The pending
character in the TXREG is then transferred to the TSR
in one T
transmission. The transmission of the Start bit, data bits
and Stop bit sequence commences immediately
following the transfer of the data to the TSR from the
TXREG.
18.1.1.3
The polarity of the transmit data can be controlled with
the CKTXP bit of the BAUDCON register. The default
state of this bit is ‘0’ which selects high true transmit
Idle and data bits. Setting the CKTXP bit to ‘1’ will invert
the transmit data resulting in low true Idle and data bits.
The CKTXP bit controls transmit data polarity only in
Asynchronous mode. In Synchronous mode the
CKTXP
Section 18.4.1.2 “Clock
18.1.1.4
The TXIF interrupt flag bit of the PIR1 register is set
whenever the EUSART transmitter is enabled and no
character is being held for transmission in the TXREG.
In other words, the TXIF bit is only clear when the TSR
is busy with a character and a new character has been
queued for transmission in the TXREG. The TXIF flag bit
is not cleared immediately upon writing TXREG. TXIF
becomes valid in the second instruction cycle following
the write execution. Polling TXIF immediately following
the TXREG write will return invalid results. The TXIF bit
is read-only, it cannot be set or cleared by software.
The TXIF interrupt can be enabled by setting the TXIE
interrupt enable bit of the PIE1 register. However, the
TXIF flag bit will be set whenever the TXREG is empty,
regardless of the state of the TXIE enable bit.
To use interrupts when transmitting data, set the TXIE
bit only when there is more data to send. Clear the
TXIE interrupt enable bit upon writing the last character
of the transmission to the TXREG.
bit
PIC16LF1904/6/7
CY
Transmitting Data
Transmit Data Polarity
Transmit Interrupt Flag
immediately following the Stop bit
has
a
Polarity”.
different
DS41569A-page 157
function.
See