PIC16LF1906T-I/SS Microchip Technology, PIC16LF1906T-I/SS Datasheet - Page 156

• Manufacturer Part Number: PIC16LF1906T-I/SS
• Description: 14KB Flash, 512B RAM, LCD, 11x10b ADC, EUSART, NanoWatt XLP 28 SSOP .209in T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1906T-I/SS

• Processor Series: PIC16LF
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Data Ram Size: 512 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 1 x 16-bit, 1 x 8-bit
• Operating Supply Voltage: 1.8 V to 5.5 V
• Mounting Style: SMD/SMT
• Package / Case: QFN-28
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: LIN, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Eeprom Size: -
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Lead Free Status / Rohs Status: Details

PIC16LF1904/6/7
FIGURE 18-2:
The operation of the EUSART module is controlled
through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCON)
These
Register 18-2
For all modes of EUSART operation, the TRIS control
bits corresponding to the RX/DT and TX/CK pins should
be set to ‘1’. The EUSART control will automatically
reconfigure the pin from input to output, as needed.
When the receiver or transmitter section is not enabled
then the corresponding RX/DT or TX/CK pin may be
used for general purpose input and output.
DS41569A-page 156
BRG16
Baud Rate Generator
SPBRGH
registers
and
RX/DT pin
SPBRGL
Register
are
+ 1
EUSART RECEIVE BLOCK DIAGRAM
detailed
18-3, respectively.
Multiplier
BRG16
SYNC
BRGH
Pin Buffer
and Control
in
1 X 0 0
X 1 1 0
X 1 0 1
x4
Register
x16 x64
F
OSC
0
0
0
18-1,
Preliminary
n
Data
Recovery
÷ n
FERR
Stop
MSb
CREN
(8)
RX9D
7
RX9
RSR Register
 2011 Microchip Technology Inc.
RCREG Register
• • •
OERR
8
1
RCIF
RCIE
Data Bus
0
START
LSb
RCIDL
Interrupt
FIFO