PIC16LF1827-E/ML Microchip Technology, PIC16LF1827-E/ML Datasheet - Page 239
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC16LF1827-E/ML
Manufacturer Part Number
PIC16LF1827-E/ML
Description
18 Pin, 7 KB Flash, 384 Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range C
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Specifications of PIC16LF1827-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC16LF
Core
PIC
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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24.2.3
The master can initiate the data transfer at any time
because it controls the SCKx line. The master
determines when the slave (Processor 2, Figure 24-5)
is to broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPxBUF register is written to. If the SPI
is only going to receive, the SDOx output could be dis-
abled (programmed as an input). The SSPxSR register
will continue to shift in the signal present on the SDIx
pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPxBUF register as
if a normal received byte (interrupts and Status bits
appropriately set).
FIGURE 24-6:
2010 Microchip Technology Inc.
Write to
SSPxBUF
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
SCKx
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
SDOx
(CKE = 0)
SDOx
(CKE = 1)
SDIx
(SMP = 0)
Input
Sample
(SMP = 0)
SDIx
(SMP = 1)
Input
Sample
(SMP = 1)
SSPxIF
SSPxSR to
SSPxBUF
SPI MASTER MODE
SPI MODE WAVEFORM (MASTER MODE)
bit 7
bit 7
bit 7
bit 7
bit 6
bit 6
bit 5
bit 5
Preliminary
bit 4
bit 4
bit 3
bit 3
The clock polarity is selected by appropriately
programming the CKP bit of the SSPxCON1 register
and the CKE bit of the SSPxSTAT register. This then,
would give waveforms for SPI communication as
shown in Figure 24-6, Figure 24-8 and Figure 24-9,
where the MSB is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user programmable to be one
of the following:
• F
• F
• F
• Timer2 output/2
• Fosc/(4 * (SSPxADD + 1))
Figure 24-6 shows the waveforms for Master mode.
When the CKE bit is set, the SDOx data is valid before
there is a clock edge on SCKx. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPxBUF is loaded with the received
data is shown.
OSC
OSC
OSC
PIC16F/LF1826/27
/4 (or T
/16 (or 4 * T
/64 (or 16 * T
bit 2
bit 2
CY
)
bit 1
bit 1
CY
CY
)
)
bit 0
bit 0
bit 0
bit 0
DS41391C-page 239
4 Clock
Modes
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