PIC16F616-H/ST Microchip Technology, PIC16F616-H/ST Datasheet - Page 96

• Manufacturer Part Number: PIC16F616-H/ST
• Description: 1.75KB Flash, 64B RAM, 6 I/O, 8MHz Internal Oscillator 14 TSSOP 4.4mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F616-H/ST

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 11
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F610/616/16HV610/616
10.4.1
In Half-Bridge mode, two pins are used as outputs to
drive push-pull loads. The PWM output signal is output
on the CCP1/P1A pin, while the complementary PWM
output signal is output on the P1B pin (see Figure 10-8).
This mode can be used for half-bridge applications, as
shown in Figure 10-9, or for full-bridge applications,
where four power switches are being modulated with
two PWM signals.
In Half-Bridge mode, the programmable dead-band delay
can be used to prevent shoot-through current in half-
bridge power devices. The value of the PDC<6:0> bits of
the PWM1CON register sets the number of instruction
cycles before the output is driven active. If the value is
greater than the duty cycle, the corresponding output
remains inactive during the entire cycle. See 10.4.6
“Programmable Dead-Band Delay mode” for more
details of the dead-band delay operations.
FIGURE 10-9:
DS41288F-page 96
Standard Half-Bridge Circuit (“Push-Pull”)
Half-Bridge Output Driving a Full-Bridge Circuit
HALF-BRIDGE MODE
EXAMPLE OF HALF-BRIDGE APPLICATIONS
P1A
P1B
P1A
P1B
FET
Driver
FET
Driver
FET
Driver
FET
Driver
Since the P1A and P1B outputs are multiplexed with
the PORT data latches, the associated TRIS bits must
be cleared to configure P1A and P1B as outputs.
FIGURE 10-8:
P1A
P1B
td = Dead-Band Delay
Note 1: At this time, the TMR2 register is equal to the
Load
V+
(2)
(2)
2: Output signals are shown as active-high.
(1)
PR2 register.
td
Pulse Width
Load
Period
td
FET
Driver
FET
Driver
EXAMPLE OF HALF-
BRIDGE PWM OUTPUT
© 2009 Microchip Technology Inc.
+
-
+
-
(1)
Period
(1)