PIC12LF1840-E/SN Microchip Technology, PIC12LF1840-E/SN Datasheet - Page 295
![7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Nano](/photos/16/3/160347/soic8_sml.jpg)
PIC12LF1840-E/SN
Manufacturer Part Number
PIC12LF1840-E/SN
Description
7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Nano
Manufacturer
Microchip Technology
Series
PIC® XLP™ 12Fr
Datasheet
1.PIC12F1840-EMF.pdf
(382 pages)
Specifications of PIC12LF1840-E/SN
Processor Series
PIC12F
Core
PIC
Program Memory Type
Flash
Program Memory Size
7 KB
Data Ram Size
256 B
Interface Type
MI2C, SPI, EUSART
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SOIC-8
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Core Processor
RISC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12LF1840-E/SN
Manufacturer:
MICRON
Quantity:
4 500
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27.0
The Capacitive Sensing (CPS) module allows for an
interaction with an end user without a mechanical
interface. In a typical application, the CPS is attached to
a pad on a Printed Circuit Board (PCB), which is
electrically isolated from the end user. When the end
user places their finger over the PCB pad, a capacitive
load is added, causing a frequency shift in the CPS
module. The CPS module requires software and at least
one timer resource to determine the change in
frequency. Key features of this module include:
• Analog MUX for monitoring multiple inputs
• Capacitive sensing oscillator
• Multiple Power modes
• High power range with variable voltage references
• Multiple timer resources
• Software control
• Operation during Sleep
FIGURE 27-1:
2011 Microchip Technology Inc.
Note
CPS0
CPS1
CPS2
CPS3
CAPACITIVE SENSING (CPS)
MODULE
1:
If CPSON = 0, disabling capacitive sensing, no channel is selected.
CAPACITIVE SENSING BLOCK DIAGRAM
CPSCH<3:0>
CPSON
Ref-
(1)
0
1
Capacitive
Oscillator
CPSOSC
CPSRM
Sensing
DAC
Ref+
CPSRNG<1:0>
CPSON
0
1
FVR
Ref.
Int.
T0CKI
Preliminary
T0XCS
CPSOUT
CPSCLK
0
1
F
OSC
SYNCC1OUT
T1GSEL<1:0>
T1CS<1:0>
/4
T1OSC/
F
F
T1CKI
T1G
OSC
OSC
0
1
/4
PIC12(L)F1840
TMR0CS
Timer0 Module
TMR0
Timer1 Module
Control Logic
Timer1 Gate
EN
TMR1H:TMR1L
Overflow
DS41441B-page 295
TMR0IF
Set
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