PIC12LF1840-E/SN Microchip Technology, PIC12LF1840-E/SN Datasheet - Page 119
![7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Nano](/photos/16/3/160347/soic8_sml.jpg)
PIC12LF1840-E/SN
Manufacturer Part Number
PIC12LF1840-E/SN
Description
7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Nano
Manufacturer
Microchip Technology
Series
PIC® XLP™ 12Fr
Datasheet
1.PIC12F1840-EMF.pdf
(382 pages)
Specifications of PIC12LF1840-E/SN
Processor Series
PIC12F
Core
PIC
Program Memory Type
Flash
Program Memory Size
7 KB
Data Ram Size
256 B
Interface Type
MI2C, SPI, EUSART
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SOIC-8
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Core Processor
RISC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12LF1840-E/SN
Manufacturer:
MICRON
Quantity:
4 500
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13.0
The PORTA pins can be configured to operate as
Interrupt-On-Change (IOC) pins. An interrupt can be
generated by detecting a signal that has either a rising
edge or a falling edge. Any individual PORTA pin, or
combination of PORTA pins, can be configured to
generate an interrupt. The interrupt-on-change module
has the following features:
• Interrupt-on-Change enable (Master Switch)
• Individual pin configuration
• Rising and falling edge detection
• Individual pin interrupt flags
Figure 13-1
13.1
To allow individual PORTA pins to generate an interrupt,
the IOCIE bit of the INTCON register must be set. If the
IOCIE bit is disabled, the edge detection on the pin will
still occur, but an interrupt will not be generated.
13.2
For each PORTA pin, a rising edge detector and a falling
edge detector are present. To enable a pin to detect a
rising edge, the associated IOCAPx bit of the IOCAP
register is set. To enable a pin to detect a falling edge,
the associated IOCANx bit of the IOCAN register is set.
A pin can be configured to detect rising and falling
edges simultaneously by setting both the IOCAPx bit
and the IOCANx bit of the IOCAP and IOCAN registers,
respectively.
FIGURE 13-1:
2011 Microchip Technology Inc.
RAx
INTERRUPT-ON-CHANGE
Enabling the Module
Individual Pin Configuration
is a block diagram of the IOC module.
IOCANx
IOCAPx
INTERRUPT-ON-CHANGE BLOCK DIAGRAM
D
CK
D
CK
R
R
Q
Q
Preliminary
Q2 Clock Cycle
individual pin detectors
From all other IOCAFx
13.3
The IOCAFx bits located in the IOCAF register are
status flags that correspond to the Interrupt-on-change
pins of PORTA. If an expected edge is detected on an
appropriately enabled pin, then the status flag for that pin
will be set, and an interrupt will be generated if the IOCIE
bit is set. The IOCIF bit of the INTCON register reflects
the status of all IOCAFx bits.
13.4
The individual status flags, (IOCAFx bits), can be
cleared by resetting them to zero. If another edge is
detected during this clearing operation, the associated
status flag will be set at the end of the sequence,
regardless of the value actually being written.
In order to ensure that no detected edge is lost while
clearing flags, only AND operations masking out known
changed bits should be performed. The following
sequence is an example of what should be performed.
EXAMPLE 13-1:
13.5
The interrupt-on-change interrupt sequence will wake
the device from Sleep mode, if the IOCIE bit is set.
If an edge is detected while in Sleep mode, the IOCAF
register will be updated prior to the first instruction
executed out of Sleep.
IOCAFx
ANDWF
MOVLW
XORWF
Interrupt Flags
Clearing Interrupt Flags
Operation in Sleep
0xff
IOCAF, W
IOCAF, F
PIC12(L)F1840
IOCIE
DS41441B-page 119
IOC Interrupt to
CPU Core
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