PIC12F635T-I/MD Microchip Technology, PIC12F635T-I/MD Datasheet - Page 122
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PIC12F635T-I/MD
Manufacturer Part Number
PIC12F635T-I/MD
Description
1.75 KB Flash, 64 RAM, 6 I/O 8 DFN 4x4mm T/R
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Specifications of PIC12F635T-I/MD
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
5
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164326 - MODULA SKT PM3 20QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFNXLT08DFN - SOCKET TRANSITION ICE 8DFN
Data Converters
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC12F635/PIC16F636/639
FIGURE 11-18:
DS41232D-page 120
LFDATA/RSSI/
MCU SPI Read Details:
1.
2.
3.
4.
5.
6.
SCLK/ALERT
Note:
CCLK/SDIO
Drive the AFE’s open collector ALERT output low.
•
Drop CS
•
•
Change LFDATA/RSSI/CCLK/SDIO connected pin to output.
•
Clock in 16-bit SPI Read sequence.
•
Change LFDATA/RSSI/CCLK/SDIO connected pin to input.
Raise CS to complete the SPI Read entry of command and address.
CS
To ensure no false clocks occur when CS drops.
AFE SCLK/ALERT becomes SCLK input.
LFDATA/RSSI/CCLK/SDIO becomes SDI input.
Driving SPI data.
Command, address and dummy data.
(output)
ALERT
The T
Configuration register data appears at 6th clock after T
LFDATA
(output)
1
CSH
(input)
(input)
SCLK
SDI
T
2
CSSC
is considered as one clock. Therefore, the
SPI READ SEQUENCE
T
SU
MSb
T
3
HD
4
16 Clocks for Read Command,
Address and Dummy Data
T
1/F
HI
SCLK
T
LO
CSH
LSb
.
T
SCCS
6
5
7.
8.
9.
10.
T
LFDATA
(output)
CS
(output)
ALERT
1
T
Drop CS.
•
•
Clock out 16-bit SPI Read result.
•
•
•
Raise CS to complete the SPI Read.
Change SCLK/ALERT back to input.
CSH
T
CS
AFE SCLK/ALERT becomes SCLK input.
LFDATA/RSSI/CCLK/SDIO becomes SDO output.
First seven bits clocked-out are dummy bits.
Next eight bits are the Configuration register data.
The last bit is the Configuration register row parity bit.
0
(input)
(output)
SCLK
T
SDO
7
CSSC
8
16 Clocks for Read Result
© 2007 Microchip Technology Inc.
T
DO
T
CSSC
9
T
LFDATA
(output)
CS
(output)
1
ALERT
10
T
CSH
T
CS
0
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