PIC12F519-E/MC Microchip Technology, PIC12F519-E/MC Datasheet - Page 3

• Manufacturer Part Number: PIC12F519-E/MC
• Description: 1.5KB Flash Program, 64B Flash Data, 8MHz Internal Oscillator 8 DFN 2X3mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F519-E/MC

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 1.5KB (1K x 12)
• Program Memory Type: FLASH
• Ram Size: 41 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-DFN
• Processor Series: PIC12F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 41 B
• Interface Type: USB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 1
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164334 - MODULE SOCKET FOR 8L 2X3MM DFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFN
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

3.0
3.1
The Program/Verify mode is entered by holding pins
ICSPCLK and ICSPDAT low while raising V
V
this mode, the user program memory and configuration
memory can be accessed and programmed in serial
fashion. Clock and data are Schmitt Trigger input in this
mode.
The sequence that enters the device into the Program-
ming/Verify mode places all other logic into the Reset
state (the MCLR pin was initially at V
that all I/Os are in the Reset state (high-impedance
inputs).
3.1.1
The programming sequence loads a word, programs,
verifies and finally increments the PC.
Program/Verify mode entry will set the address to
0x7FF.
increment the PC. The available commands are shown
in Table 3-1.
FIGURE 3-1:
TABLE 3-1:
© 2007 Microchip Technology Inc.
IL
Load Data
Read Data
Increment Address
Begin Programming
End Programming
Bulk Erase Program Memory
to V
RB0
(ICSPDAT)
(ICSPCLK)
RB1
DD
V
V
COMMANDS AND
ALGORITHMS
Program/Verify Mode
The
DD
PP
. Then raise V
PROGRAMMING
Increment
Command
COMMAND MAPPING LOAD DATA
T
ENTERING HIGH
VOLTAGE PROGRAM/
VERIFY MODE
PPDP
PP
Address
from V
T
HLD
0
IL
to V
IL
command
). This means
IHH
DD
. Once in
pin from
(MSb ... LSb)
X X 0 0 1 0
X X 0 1 0 0
X X 0 1 1 0
X X 1 0 0 0
X X 1 1 1 0
X X 1 0 0 1
Mapping
will
3.1.2
The RB1 pin is used as a clock input pin, and the RB0
pin is used for entering command bits and data input/
output during serial operation. To input a command, the
clock pin (RB1) is cycled 6 times. Each command bit is
latched on the falling edge of the clock with the Least
Significant bit (LSb) of the command being input first.
The data on pin RB0 is required to have a minimum
setup and hold time of 100 ns with respect to the falling
edge of the clock. Commands that have data associ-
ated with them (Read and Load) are specified to have
a minimum delay of 1 µs between the command and
the data. After this delay the clock pin is cycled 16 times
with the first cycle being a Start bit and the last cycle
being a Stop bit. Data is also input and output LSb first,
with data input being latched on the falling edge of the
clock and data output being driven on the rising edge of
the clock. Therefore, during a Read operation the LSb
will be transmitted onto pin RB0 on the rising edge of
the second cycle, and during a Load operation the LSb
will be latched on the falling edge of the second cycle.
A minimum 1 µs delay is also specified between con-
secutive commands; except the “End Programming”
command which requires a 100 µs delay. Because this
is a 12-bit core, the two MSbs of the data word are
ignored. The commands that are available are
described in Table 3-1.
Value
Hex
E
2
4
6
8
9
start_bit, data (14), stop_bit
start_bit, data (14), stop_bit
SERIAL PROGRAM/VERIFY
OPERATION
PIC12F519
Data
DS41316B-page 3