PIC12F1840T-I/SN Microchip Technology, PIC12F1840T-I/SN Datasheet - Page 375
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PIC12F1840T-I/SN
Manufacturer Part Number
PIC12F1840T-I/SN
Description
7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 SOI
Manufacturer
Microchip Technology
Series
PIC® XLP™ 12Fr
Datasheet
1.PIC12F1840-EMF.pdf
(382 pages)
Specifications of PIC12F1840T-I/SN
Core Processor
RISC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (0.154", 3.90mm Width)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12F1840T-I/SN
Manufacturer:
MICROCHIP
Quantity:
3 000
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Extended Instruction Set
F
Fail-Safe Clock Monitor....................................................... 59
Firmware Instructions........................................................ 307
Fixed Voltage Reference (FVR) ........................................ 123
Flash Program Memory ...................................................... 97
FSR Register ................ 24, 25, 26, 27, 28, 29, 30, 31, 32, 33
FVRCON (Fixed Voltage Reference Control) Register ..... 124
I
I
INDF Register ............... 24, 25, 26, 27, 28, 29, 30, 31, 32, 33
Indirect Addressing ............................................................. 37
Instruction Format ............................................................. 308
Instruction Set ................................................................... 307
2011 Microchip Technology Inc.
2
C Mode (MSSPx)
ADDFSR ................................................................... 311
Fail-Safe Condition Clearing ....................................... 59
Fail-Safe Detection ..................................................... 59
Fail-Safe Operation..................................................... 59
Reset or Wake-up from Sleep..................................... 59
Associated Registers ................................................ 124
Erasing...................................................................... 102
Modifying................................................................... 106
Writing....................................................................... 102
Acknowledge Sequence Timing................................ 251
Bus Collision
Effects of a Reset...................................................... 252
I
Master Mode
Multi-Master Communication, Bus Collision and
Multi-Master Mode .................................................... 252
Read/Write Bit Information (R/W Bit) ........................ 228
Slave Mode
Sleep Operation ........................................................ 252
Stop Condition Timing............................................... 251
ADDLW ..................................................................... 311
ADDWF..................................................................... 311
ADDWFC .................................................................. 311
ANDLW ..................................................................... 311
ANDWF..................................................................... 311
BRA........................................................................... 312
CALL ......................................................................... 313
CALLW...................................................................... 313
LSLF ......................................................................... 315
LSRF......................................................................... 315
MOVF........................................................................ 315
MOVIW ..................................................................... 316
MOVLB ..................................................................... 316
MOVWI ..................................................................... 317
OPTION .................................................................... 317
RESET ...................................................................... 317
SUBWFB................................................................... 319
2
C Clock Rate w/BRG.............................................. 259
Associated Registers
Reception.......................................................... 293
Transmission .................................................... 292
During a Repeated Start Condition ................... 256
During a Stop Condition.................................... 257
Operation .......................................................... 243
Reception.......................................................... 249
Start Condition Timing .............................. 245, 246
Transmission .................................................... 247
Arbitration ......................................................... 252
Transmission .................................................... 233
Receive..................................................... 293
Transmit.................................................... 292
Preliminary
INTCON Register................................................................ 83
Internal Oscillator Block
Internal Sampling Switch (R
Internet Address ............................................................... 379
Interrupt-On-Change......................................................... 119
Interrupts ............................................................................ 77
INTOSC Specifications ..................................................... 337
IOCAF Register ................................................................ 120
IOCAN Register ................................................................ 120
IOCAP Register ................................................................ 120
L
LATA Register .................................................................. 116
Load Conditions................................................................ 335
LSLF ................................................................................. 315
LSRF ................................................................................ 315
M
Master Synchronous Serial Port. See MSSPx
MCLR ................................................................................. 72
MDCARH Register............................................................ 186
MDCARL Register ............................................................ 187
MDCON Register.............................................................. 184
MDSRC Register .............................................................. 185
Memory Organization ......................................................... 15
TRIS ......................................................................... 320
BCF .......................................................................... 312
BSF........................................................................... 312
BTFSC...................................................................... 312
BTFSS ...................................................................... 312
CALL......................................................................... 313
CLRF ........................................................................ 313
CLRW ....................................................................... 313
CLRWDT .................................................................. 313
COMF ....................................................................... 313
DECF........................................................................ 313
DECFSZ ................................................................... 314
GOTO ....................................................................... 314
INCF ......................................................................... 314
INCFSZ..................................................................... 314
IORLW ...................................................................... 314
IORWF...................................................................... 314
MOVLW .................................................................... 316
MOVWF.................................................................... 316
NOP.......................................................................... 317
RETFIE..................................................................... 318
RETLW ..................................................................... 318
RETURN................................................................... 318
RLF........................................................................... 318
RRF .......................................................................... 319
SLEEP ...................................................................... 319
SUBLW..................................................................... 319
SUBWF..................................................................... 319
SWAPF..................................................................... 320
XORLW .................................................................... 320
XORWF .................................................................... 320
INTOSC
Associated Registers................................................ 121
ADC .......................................................................... 132
Associated registers w/ Interrupts .............................. 88
Configuration Word w/ Clock Sources........................ 63
Configuration Word w/ Reference Clock Sources ...... 67
TMR1........................................................................ 167
Internal........................................................................ 72
Data ............................................................................ 17
Specifications ................................................... 337
PIC12(L)F1840
SS
) Impedance ..................... 137
DS041441B-page 375
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