PIC12F1840T-I/SN Microchip Technology, PIC12F1840T-I/SN Datasheet - Page 334
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC12F1840T-I/SN
Manufacturer Part Number
PIC12F1840T-I/SN
Description
7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 SOI
Manufacturer
Microchip Technology
Series
PIC® XLP™ 12Fr
Datasheet
1.PIC12F1840-EMF.pdf
(382 pages)
Specifications of PIC12F1840T-I/SN
Core Processor
RISC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (0.154", 3.90mm Width)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12F1840T-I/SN
Manufacturer:
MICROCHIP
Quantity:
3 000
- Current page: 334 of 382
- Download datasheet (4Mb)
PIC12(L)F1840
30.6
DS41441B-page 334
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C T
TH01
TH02
TH03
TH04
TH05
TH06
TH07
Legend:
Note 1: I
Param
No.
2: T
3: T
Thermal Considerations
P
DD
INTERNAL
A
J
T
Sym.
P
TBD = To Be Determined
P
= Junction Temperature.
JMAX
= Ambient Temperature.
PD
DER
is current to run the chip alone without driving any load on the output pins.
JA
JC
I
/
O
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Case
Maximum Junction Temperature
Power Dissipation
Internal Power Dissipation
I/O Power Dissipation
Derated Power
A
Characteristic
+125°C
Preliminary
Typ.
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
150
—
—
—
—
Units
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C
W
W
W
W
8-pin PDIP package
8-pin DFN 3X3mm package
14-pin PDIP package
14-pin SOIC package
14-pin TSSOP 4x4mm package
16-pin QFN 4X4mm package
8-pin PDIP package
8-pin DFN 3X3mm package
14-pin PDIP package
14-pin SOIC package
14-pin TSSOP 4x4mm package
16-pin QFN 4X4mm package
PD = P
P
8-pin SOIC package
8-pin SOIC package
P
P
INTERNAL
I
DER
/
O
= (I
= PD
INTERNAL
2011 Microchip Technology Inc.
OL
= I
MAX
* V
DD
Conditions
(T
OL
+ P
x V
J
) + (I
- T
DD
I
/
O
A
(1)
)/
OH
JA
(2)
* (V
DD
- V
OH
))
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