PIC12F1840T-I/SN Microchip Technology, PIC12F1840T-I/SN Datasheet - Page 309

• Manufacturer Part Number: PIC12F1840T-I/SN
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 SOI
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 12Fr

Specifications of PIC12F1840T-I/SN

• Core Processor: RISC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 29-3:
 2011 Microchip Technology Inc.
ADDWF
ADDWFC
ANDWF
ASRF
LSLF
LSRF
CLRF
CLRW
COMF
DECF
INCF
IORWF
MOVF
MOVWF
RLF
RRF
SUBWF
SUBWFB
SWAPF
XORWF
DECFSZ
INCFSZ
BCF
BSF
BTFSC
BTFSS
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
MOVLB
MOVLP
MOVLW
SUBLW
XORLW
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
Mnemonic,
Operands
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one
is executed as a NOP.
additional instruction cycle.
f, d
f, d
f, d
f, d
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f, b
f, b
f, b
f, b
k
k
k
k
k
k
k
k
PIC12F/LF1840 ENHANCED INSTRUCTION SET
Add W and f
Add with Carry W and f
AND W with f
Arithmetic Right Shift
Logical Left Shift
Logical Right Shift
Clear f
Clear W
Complement f
Decrement f
Increment f
Inclusive OR W with f
Move f
Move W to f
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Subtract with Borrow W from f
Swap nibbles in f
Exclusive OR W with f
Decrement f, Skip if 0
Increment f, Skip if 0
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Add literal and W
AND literal with W
Inclusive OR literal with W
Move literal to BSR
Move literal to PCLATH
Move literal to W
Subtract W from literal
Exclusive OR literal with W
BYTE-ORIENTED FILE REGISTER OPERATIONS
Description
BIT-ORIENTED FILE REGISTER OPERATIONS
BYTE ORIENTED SKIP OPERATIONS
BIT-ORIENTED SKIP OPERATIONS
Preliminary
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1(2)
1(2)
1
1
1 (2)
1 (2)
1
1
1
1
1
1
1
1
Cycles
00
00
01
01
01
01
11
11
11
00
11
11
11
11
MSb
00
11
00
11
11
11
00
00
00
00
00
00
00
00
00
00
00
11
00
00
14-Bit Opcode
PIC12(L)F1840
1011
1111
00bb
01bb
10bb
11bb
1110
1001
1000
0000
0001
0000
1100
1010
0111
1101
0101
0111
0101
0110
0001
0001
1001
0011
1010
0100
1000
0000
1101
1100
0010
1011
1110
0110
dfff
dfff
bfff
bfff
bfff
bfff
kkkk
kkkk
kkkk
001k
1kkk
kkkk
kkkk
kkkk
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
1fff
dfff
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
ffff
ffff
ffff
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
ffff
ffff
ffff
ffff
ffff
ffff
ffff
00xx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
LSb
DS41441B-page 309
C, DC, Z
C, DC, Z
Z
C, Z
C, Z
C, Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
C, DC, Z
Z
C, DC, Z
Z
Z
C, DC, Z
Z
Affected
Status
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1, 2
1, 2
2
2
1, 2
1, 2
Notes