ICS1892Y-10T IDT, Integrated Device Technology Inc, ICS1892Y-10T Datasheet - Page 125
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ICS1892Y-10T
Manufacturer Part Number
ICS1892Y-10T
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.ICS1892Y-10T.pdf
(148 pages)
Specifications of ICS1892Y-10T
Lead Free Status / RoHS Status
Not Compliant
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10.5.2 Timing for Transmit Clock (TXCLK) Pin
ICS1892, Rev. D, 2/26/01
TXCLK
Table 10-9
interfaces.
Table 10-9. Transmit Clock Timing
Figure 10-2. Transmit Clock Timing Diagram
Period
Time
t2a
t2b
t2c
t2d
ICS1892
t1
TXCLK Duty Cycle
TXCLK Period
TXCLK Period
TXCLK Period
TXCLK Period
Figure 10-2
lists the significant time periods for signals on the Transmit Clock (TXCLK) pin for the various
Parameter
shows the timing diagram for the time periods.
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
100M MII (100Base-TX)
10M MII (10Base-T)
100M Symbol Interface (100Base-TX)
10M Symbol Interface (10Base-T)
t1
Conditions
125
t2x
–
Chapter 10 DC and AC Operating Conditions
Min.
35
–
–
–
–
Typ.
400
100
50
40
40
February 26, 2001
Max.
65
–
–
–
–
Units
ns
ns
ns
ns
%
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