HY82563EB S L7WG Intel, HY82563EB S L7WG Datasheet - Page 27
HY82563EB S L7WG
Manufacturer Part Number
HY82563EB S L7WG
Description
Manufacturer
Intel
Datasheet
1.HY82563EB_S_L7WG.pdf
(52 pages)
Specifications of HY82563EB S L7WG
Lead Free Status / RoHS Status
Compliant
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4.4.2.2
4.4.3
Figure 3. 82563EB/82564EB power up sequencing with external regulators
Table 21. 3.3V External Power Supply Parameters
External LVR Power down Sequencing
Internally-Generated Power Delivery
There are no specific power down sequencing and tracking requirements for the 82563EB/
82564EB silicon. The risk of latch-up or electrical overstress is small because only the charge
stored in the decoupling capacitors is left in the system.
The 82563EB/82564EB has two internal linear voltage regulator controllers. The controllers use
external transistors to generate 2 of the 3 required voltages: 1.9V (nominal) and 1.2V (nominal).
These two voltages are stepped-down from a 3.3V source.
Operational Range
Monotonicity
Rise Time
Slope
Title
V
82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon
Max
Difference ≤
0.5 V
Ramp rate at any given time between
Voltage range for normal operating
Max: 0.8*V(max)/Rise time (min)
Min: 0.8*V(min)/Rise time (max)
Time from 10% to 90% mark
Voltage dip allowed in ramp
10% and 90%
Description
conditions
Max
Difference ≤
0.5 V
Min
3.0
2
-
-
1500
Max
200
300
3.6
1.2 V
3.3 V
1.9 V
t
mV/ms
Units
mV
ms
V
21
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