HY82563EB S L7WG Intel, HY82563EB S L7WG Datasheet - Page 15

• Manufacturer Part Number: HY82563EB S L7WG
• Manufacturer: Intel

Specifications of HY82563EB S L7WG

• Lead Free Status / RoHS Status: Compliant

3.7
3.8
Table 6. Reset and Power Down Signals
Table 7. JTAG Signals
Reset, Power Down, and Initialization Signals
JTAG and IEEE Interface
PHY_PWR_GOOD
PHY_RESET_N
PHY_SLEEP
TEST_JTAG
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
Signal Name
Signal Name
82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon
100
1
99
3
Pin
83
81
80
95
Pin
I
I PU
O
I PU
Type
I
I
I (T)
I PU
Type
TTL
TTL
TTL3
TTL
Type
Sub-
TTL
TTL
TTL
TTL
Sub-
Type
JTAG Clock
This pin should be pulled high through a 1 to 10 KΩ 5% resistor
in normal operation.
JTAG Serial Data Input
If not using JTAG, this pin may be pulled high through a 1 to
10 KΩ 5% resistor
JTAG Serial Data Output
JTAG TMS Input
If not using JTAG, this pin may be pulled high through a 1 to
10 KΩ 5% resistor
Power Good (Power-On Reset)
The PHY_PWR_GOOD signal indicates good power is
available for The device. When set to 0b, the entire chip will be
held in a reset state.
Reset
When set to 0b, resets the device, including PHY and Kumeran
logic. Needs an external pull-up resistor if the signal isn’t
continuously being driven from an external source.
Sleep / Power Down
This will power down the PHY and the Kumeran of both ports.
Needs an external pull-down resistor, if the signal isn’t
continuously being driven from an external source.
Enable JTAG Pin Control
This pin should be pulled high through a 1 to 10 KΩ 5% resistor
in normal operation.
Description
Description
9