FLLXT971ABC.A4 Intel, FLLXT971ABC.A4 Datasheet - Page 46

• Manufacturer Part Number: FLLXT971ABC.A4
• Manufacturer: Intel

Specifications of FLLXT971ABC.A4

• Lead Free Status / RoHS Status: Not Compliant

Intel
5.6.7.2
5.7
5.7.1
46
Figure 14. 100BASE-X Frame Format
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Internal Digital Loopback (Test Loopback)
A test loopback function is provided for diagnostic testing of the LXT971A Transceiver. During
test loopback, twisted-pair and fiber interfaces are disabled. Data transmitted by the MAC is
internally looped back by the LXT971A Transceiver and returned to the MAC.
Test loopback is available for both 100BASE-TX and 10BASE-T operation, and is enabled by
setting the following register bits:
Test loopback is also available for 100BASE-FX operation. Test loopback in this mode is enabled
by setting Register bit 0.14 = 1 and tying the SD input to an LVPECL logic High value (2.4 V).
100 Mbps Operation
100BASE-X Network Operations
During 100BASE-X operation, the LXT971A Transceiver transmits and receives 5-bit symbols
across the network link.
Figure 14
not actively transmitting data, the LXT971A Transceiver sends out Idle symbols on the line.
As
LXT971A Transceiver detects the start of preamble, it transmits a Start-of-Stream Delimiter (SSD,
symbols J and K) to the network. It then encodes and transmits the rest of the packet, including the
balance of the preamble, the SFD, packet data, and CRC.
Once the packet ends, the LXT971A Transceiver transmits the End-of-Stream Delimiter (ESD,
symbols T and R) and then returns to transmitting Idle symbols.
For details on the symbols used, see 4B/5B coding listed in
Replaced by
/J/K/ code-groups
Start-of-Stream
Delimiter (SSD)
•
•
•
P0
Figure 14
Register bit 0.14 = 1 (Setting to enable loopback mode)
Register bit 0.8 = 1 (Setting for full-duplex mode)
Register bit 0.12 = 0. (Disable auto-negotiation.)
64-Bit Preamble
P1
(8 Octets)
shows the structure of a standard frame packet in 100BASE-X mode. When the MAC is
P6
shows, the MAC starts each transmission with a preamble pattern. As soon as the
Delimiter (SFD)
Start-of-Frame
SFD
DA
Address (6 Octets each)
Destination and Source
DA
SA
SA
Packet Length
L1
(2 Octets)
L2
(Pad to minimum packet size)
D0
Data Field
D1
Table 14, “4B/5B Coding” on page
Dn
Frame Check Field
(4 Octets)
CRC
Document Number: 249414-003
End-of-Stream Delimiter (ESD)
Revision Date: June 18, 2004
/T/R/ code-groups
Replaced by
B3466-01
InterFrame Gap / Idle Code
I0
(> 12 Octets)
Datasheet
IFG
51.