FLLXT971ABC.A4 Intel, FLLXT971ABC.A4 Datasheet - Page 31

• Manufacturer Part Number: FLLXT971ABC.A4
• Manufacturer: Intel

Specifications of FLLXT971ABC.A4

• Lead Free Status / RoHS Status: Not Compliant

5.2.3.2
Datasheet
Document Number: 249414-003
Revision Date: June 18, 2004
Figure 6. Intel
5.2.3.1.3 MII Interrupts
Figure 6
pin (MDINT_L) and two dedicated interrupt registers, Register 18 and Register 19.
Hardware Control Interface
The LXT971A Transceiver provides a Hardware Control Interface for applications where the
MDIO is not desired. The Hardware Control Interface uses the hardware configuration pins to set
device configuration. For details, see
page
•
•
Even X Status Reg
Even X Mask Reg
Register 18 provides interrupt enable and mask functions. Setting Register bit 18.1 = 1 enables
the device to request interrupt via the MDINT_L pin. An active Low on this pin indicates a
status change on the LXT971A Transceiver. Interrupts may be caused by any of the following
four conditions:
Register 19 provides the interrupt status.
®
37.
— Auto-negotiation complete
— Speed status change
— Duplex status change
— Link status change
Force Interrupt
LXT971A Transceiver MII Interrupt Logic
shows the MII interrupt logic. The LXT971A Transceiver provides a hardware interrupt
Intel
®
AND
Section 5.4.4, “Hardware Configuration Settings” on
LXT971A Single-Port 10/100 Mbps PHY Transceiver
OR
Interrupt Enable
NAND
Interrupt Pin
MDINT_L
B3474-01
31