FLLXT971ABC.A4 Intel, FLLXT971ABC.A4 Datasheet - Page 43

• Manufacturer Part Number: FLLXT971ABC.A4
• Manufacturer: Intel

Specifications of FLLXT971ABC.A4

• Lead Free Status / RoHS Status: Not Compliant

5.6.2
5.6.3
Datasheet
Document Number: 249414-003
Revision Date: June 18, 2004
Figure 12. Clocking for Link Down Clock Transition
Transmit Enable
The MAC must assert TX_EN the same time as the first nibble of preamble and de-assert TX_EN
after the last nibble of the packet.
Receive Data Valid
The LXT971A Transceiver asserts RX_DV when it receives a valid packet. Timing changes
depend on line operating speed:
•
•
For 100BASE-TX links, RX_DV is asserted from the first nibble of preamble to the last nibble
of the data packet.
For 10BASE-T links, the entire preamble is truncated. RX_DV is asserted with the first nibble
of the Start of Frame Delimiter (SFD) “5D” and remains asserted until the end of the packet.
RX_CLK
TX_CLK
Intel
Clock
Any
Clock transition time does not exceed
2X the nominal clock period:
10 Mbps = 2.5 MHz
100 Mbps = 25 MHz
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Link-Down Condition/Auto-Negotiate Enabled
2.5 MHz
Clock
B3503-01
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