KS8721B A4 Micrel Inc, KS8721B A4 Datasheet - Page 9

• Manufacturer Part Number: KS8721B A4
• Manufacturer: Micrel Inc

Specifications of KS8721B A4

• Lead Free Status / RoHS Status: Not Compliant

Strapping Options
Note 1.
Note 2.
Note 3.
March 2006
Pin Number
Pin Number
Pin Number
11
11
21
21
22
22
6,5,
6,5,
6,5,
6,5,
6,5,
9
9
4,3
4,3
4,3
4,3
4,3
25
25
25
25
27
27
27
27
27
28
28
28
28
28
29
29
29
29
29
30
30
30
30
30
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
Strap-in is latched during power-up or reset.
Ipu = input w/ internal pull-up
Ipd = input w/ internal pull-down
Ipd/O = input w/ internal pull-down during reset, output pin otherwise
Ipu/O = input w/ internal pull-up during reset, output pin otherwise
PU = strap pin pull-up
PD = strap pin pull-down
Some devices may drive MII pins that are designated as output (PHY) on power up, resulting in incorrect strapping values latched in at reset.
It is rcommended that an external pull down via 1kΩ resistor be used in these applications to augment the 8721's internal pull down.
PHYAD[4:1]/
PHYAD[4:1]/
PHYAD[4:1]/
PHYAD[4:1]/
PHYAD[4:1]/
PCS_LPBK/
PCS_LPBK/
PCS_LPBK/
PCS_LPBK/
ISO/RXER
ISO/RXER
ISO/RXER
ISO/RXER
Pin Name
Pin Name
Pin Name
RMII_BTB
RMII_BTB
RMII_BTB
RMII_BTB
NWAYEN/
NWAYEN/
NWAYEN/
NWAYEN/
NWAYEN/
RMII/COL
RMII/COL
RMII/COL
RMII/COL
DUPLEX/
DUPLEX/
DUPLEX/
DUPLEX/
DUPLEX/
PHYAD0/
PHYAD0/
PHYAD0/
PHYAD0/
RXD[0:3]
RXD[0:3]
RXD[0:3]
RXD[0:3]
RXD[0:3]
SPD100/
SPD100/
SPD100/
SPD100/
SPD100/
No FEF/
No FEF/
No FEF/
No FEF/
No FEF/
RXDV
RXDV
RXDV
RXDV
RXDV
LED1
LED1
LED1
LED1
LED1
LED2
LED2
LED2
LED2
LED2
LED3
LED3
LED3
LED3
LED3
INT#
INT#
INT#
INT#
CRS
CRS
CRS
PD#
PD#
PD#
PD#
PD#
(Note 1)
Type
Type
Type
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu
Ipu
Ipu
Ipu
Ipu
(Note 2)
(Note 2)
Description
Description
PHY Address latched at power-up/reset. The default PHY address is 00001.
PHY Address latched at power-up/reset. The default PHY address is 00001.
PHY Address latched at power-up/reset. The default PHY address is 00001.
PHY Address latched at power-up/reset. The default PHY address is 00001.
PHY Address latched at power-up/reset. The default PHY address is 00001.
Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enable RMII_BTB mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enable RMII_BTB mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enable RMII_BTB mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enable RMII_BTB mode at power-up/reset. PD (default) = Disable, PU = Enable.
Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default)
Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default)
Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default)
Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default)
Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default)
= 100Mbps. If SPD100 is asserted during power-up/reset, this pin also latched as
= 100Mbps. If SPD100 is asserted during power-up/reset, this pin also latched as
= 100Mbps. If SPD100 is asserted during power-up/reset, this pin also latched as
= 100Mbps. If SPD100 is asserted during power-up/reset, this pin also latched as
= 100Mbps. If SPD100 is asserted during power-up/reset, this pin also latched as
the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0
the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0
the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0
the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0
the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0
means no Far_End _Fault.)
means no Far_End _Fault.)
means no Far_End _Fault.)
means no Far_End _Fault.)
means no Far_End _Fault.)
Latched into Register 0h bit 8 during power-up/reset. PD = Half duplex, PU
Latched into Register 0h bit 8 during power-up/reset. PD = Half duplex, PU
Latched into Register 0h bit 8 during power-up/reset. PD = Half duplex, PU
Latched into Register 0h bit 8 during power-up/reset. PD = Half duplex, PU
Latched into Register 0h bit 8 during power-up/reset. PD = Half duplex, PU
(default) = Full duplex. If Duplex is pulled up during reset, this pin also latched as
(default) = Full duplex. If Duplex is pulled up during reset, this pin also latched as
(default) = Full duplex. If Duplex is pulled up during reset, this pin also latched as
(default) = Full duplex. If Duplex is pulled up during reset, this pin also latched as
(default) = Full duplex. If Duplex is pulled up during reset, this pin also latched as
the Duplex support in register 4h.
the Duplex support in register 4h.
the Duplex support in register 4h.
the Duplex support in register 4h.
the Duplex support in register 4h.
Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/
Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/
Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/
Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/
Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/
reset. PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation.
reset. PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation.
reset. PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation.
reset. PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation.
reset. PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation.
Power Down Enable. PU (default) = Normal operation, PD = Power down mode.
Power Down Enable. PU (default) = Normal operation, PD = Power down mode.
Power Down Enable. PU (default) = Normal operation, PD = Power down mode.
Power Down Enable. PU (default) = Normal operation, PD = Power down mode.
Power Down Enable. PU (default) = Normal operation, PD = Power down mode.
9
M9999-030106