KS8721B A4 Micrel Inc, KS8721B A4 Datasheet - Page 12

• Manufacturer Part Number: KS8721B A4
• Manufacturer: Micrel Inc

Specifications of KS8721B A4

• Lead Free Status / RoHS Status: Not Compliant

During auto-negotiation, the contents of Register 4, coded in Fast Link Pulse (FLP), will be sent to its link partner under the
conditions of power-on, link-loss or re-start. At the same time, the KS8721B/BT will monitor incoming data to determine its
mode of operation. Parallel detection circuit will be enabled as soon as either 10BaseT NLP (Normal Link Pulse) or 100Ba-
seTX idle is detected. The operation mode is confi gured based on the following priority:
When the KS8721B/BT receives a burst of FLP from its link partner with 3 identical link code words (ignoring acknowledge
bit), it will store these code words in Register 5 and wait for the next 3 identical code words. Once the KS8721B/BT detects
the second code words, it then confi gures itself according to above-mentioned priority. In addition, the KS8721B/BT also
checks 100BaseTX idle or 10BaseT NLP symbol. If either is detected, the KS8721B/BT automatically confi gures to match
the detected operating speed.
MII Management Interface
The KS8721B/BT supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input / Output
(MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the KS8721B/BT. The MDIO
interface consists of the following:
The INTPRT pin functions as a management data interrupt in the MII. An active Low or High in this pin indicates a status
change on the KS8721B/BT based on 1fh.9 level control. Register bits at 1bh[15:8] are the interrupt enable bits. Register
bits at 1bh[7:0] are the interrupt condition bits. This interrupt is cleared by reading Register 1bh.
MII Data Interface
The data interface consists of separate channels for transmitting data from a 10/100 802.3 compliant Media Access Control-
ler (MAC) to the KS8721B/BT, and for receiving data from the line. Normal data transmission is implemented in 4B Nibble
Mode (4-bit wide nibbles).
Transmit Clock (TXC): The transmit clock is normally generated by the KS8721B/BT from an external 25MHz reference
source at the X1 input. The transmit data and control signals must always be synchronized to the TXC by the MAC. The
KS8721B/BT normally samples these signals on the rising edge of the TXC.
Receive Clock (RXC): For 100BaseTX links, the receive clock is continuously recovered from the line. If the link goes down,
and auto-negotiation is disabled, the receive clock operates off the master input clock (X1 or TXC). For 10BaseT links, the
receive clock is recovered from the line while carrier is active, and operates from the master input clock when the line is
idle. The KS8721B/BT synchronizes the receive data and control signals on the falling edge of RXC in order to stabilize the
signals at the rising edge of the clock with 10ns setup and hold times.
Transmit Enable: The MAC must assert TXEN at the same time as the fi rst nibble of the preamble, and de-assert TXEN
after the last bit of the packet.
Receive Data Valid: The KS8721B/BT asserts RXDV when it receives a valid packet. Line operating speed and MII mode
will determine timing changes in the following way:
Error Signals: Whenever the KS8721B/BT receives an error symbol from the network, it asserts RXER and drives “1110”
(4B) on the RXD pins. When the MAC asserts TXER, the KS8721B/BT will drive “H” symbols (a Transmit Error defi ne in the
IEEE 802.3 4B/5B code group) out on the line to force signaling errors.
Carrier Sense (CRS): For 100TX links, a start-of-stream delimiter, or /J/K symbol pair causes assertion of Carrier Sense
(CRS). An end-of-stream delimiter, or /T/R symbol pair causes de-assertion of CRS. The PMA layer will also de-assert CRS
if IDLE symbols are received without /T/R, yet in this case RXER will be asserted for one clock cycle when CRS is de-as-
serted. For 10T links, CRS assertion is based on reception of valid preamble, and de-assertion on reception of an end-of-
frame (EOF) marker.
M9999-030106
Priority 1: 100BaseTX, full-duplex
Priority 2: 100BaseTX, half-duplex
Priority 3: 10BaseT, full-duplex
Priority 4: 10BaseT, half-duplex
• A physical connection including a data line (MDIO), a clock line (MDC) and an optional interrupt line (INTRPT)
• A specifi c protocol that runs across the above-mentioned physical connection and it also allows one controller to
• An internal addressable set of fourteen 16-bit MDIO registers. Register [0:6] are required and their functions are
• For 100BaseTX link with the MII in 4B mode, RXDV is asserted from the fi rst nibble of the preamble to the last
• For 10BaseT links, the entire preamble is truncated. RXDV is asserted with the fi rst nibble of the SFD “ 5D” and
communicate with multiple KS8721B/BT devices. Each KS8721B/BT assigned an MII address between 0 and 31
by the PHYAD inputs.
specifi ed by the IEEE 802.3 specifi cations. Additional registers are provided for expanded functionality.
nibble of the data packet.
remains asserted until the end of the packet.
12
March 2006