DJLXT905LC.C2 831645 Intel, DJLXT905LC.C2 831645 Datasheet - Page 29
DJLXT905LC.C2 831645
Manufacturer Part Number
DJLXT905LC.C2 831645
Description
Manufacturer
Intel
Datasheet
1.DJLXT905LC.C2_831645.pdf
(40 pages)
Specifications of DJLXT905LC.C2 831645
Lead Free Status / RoHS Status
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4.2
Datasheet
Document Number: 249271
Revision Number: 004
Revision Date: 19-Oct-2005
TPIP/TPIN
Figure 15. Mode 2 RCLK/Start-of-Frame
Figure 16. Mode 2 RCLK/End-of-Frame Timing
NOTE:
1. RXD changes at the rising edge of RCLK. Mode 2 samples the controller at the falling edge .
NOTE:
TPIP/TPIN
1. RXD changes at the rising edge of RCLK. Mode 2 samples the controller at the falling edge .
RCLK
RCLK
RXD
CD
RXD
CD
Timing Diagrams for Mode 2 (MD1 = Low, MD0 = High)
Timing diagrams for Mode 2 include
1
1
0
t
CD
0
1
1
t
RD
0
0
1
t
1
DATA
1
0
0
0
1
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
1
1
0
0
0
1
1
Figure 15
0
t
1
0
RDS
1
1
0
t
1
CDOFF
through
0
1
0
1
0
0
t
Figure
RDH
0
1
0
0
Mode 2 RCLK EoF
18.
0
1
PTM2_2
1
0
0
1
1
1
0
1
0
1
29
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