L-ET1011C2-C-D LSI, L-ET1011C2-C-D Datasheet - Page 72

• Manufacturer Part Number: L-ET1011C2-C-D
• Manufacturer: LSI

Specifications of L-ET1011C2-C-D

• Number Of Receivers: 1
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Lead Free Status / RoHS Status: Compliant

Gigabit Ethernet Transceiver
Timing Specifications
Internal Delay
Table 71. RGMII 1000Base-T Receive Timing
1. The PHY uses internal delay to compensate by delaying both incoming and outgoing clocks by ~2.0 ns.
2. For 10Base-T and 100Base-TX, Tcyc scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
3. Duty cycle may be shrunk/stretched during speed changes or while transitioning to a received packet’s clock domain as long as minimum duty cycle is not
72
violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned between.
Symbol
TsetupT
TsetupR
Duty_G
Duty_T
TholdT
TholdR
Tr/Tf
AT TRANSMITTER
Tcyc
RX_CLK (RXC)
(at transmitter)
RXD[8:5][3:0]
RXD[8:5][3:0]
rXD[7:4][3:0]
RXD[7:4][3:0]
RXC
AT TRANSMITTER
RX_EN
(RX_CTL)
RX_CLK (RXC)
(at receiver)
RXC
AT RECEIVER
AT RECEIVER
RXD[3:0]
RX_CLK
RX_CLK
RX_CTL
Data to Clock Output Setup (at transmitter—integrated
Clock to Data Output Hold (at transmitter—integrated
Data to Clock Input Setup (at receiver—integrated delay)
Data to Clock Input Hold (at receiver—integrated delay)
Clock Cycle Duration
Duty Cycle for Gigabit
Duty Cycle for 10Base-T/100Base-TX
Rise/Fall Time (20%—80%)
delay)
delay)
Figure 20. RGMII 1000Base-T Receive Timing—Internal Delay
1
1
(continued)
RXD[3:0]
RXD[7:4]
RXD[4]
RX_DV
TX_EN
2
3
Parameter
RXD[8:5]
RXD[7:4]
RXD[9]
RXERR
RXD[3:0]
RX_ER
3
TsetupT
TsetupR
TSKEWT
1
1
Min
1.2
1.2
1.0
1.0
7.2
45
40
—
Typ
2.0
2.0
2.0
2.0
50
50
—
8
TholdT
TholdR
TSKEWR
September 2007
Max
0.75
8.8
—
—
—
—
55
60
LSI Corporation
RXC WITH
INTERNAL
DELAY
ADDED
RXC with
internal
delay
added
Unit
ns
ns
ns
ns
ns
ns
%
%