L-ET1011C2-C-D LSI, L-ET1011C2-C-D Datasheet - Page 28

• Manufacturer Part Number: L-ET1011C2-C-D
• Manufacturer: LSI

Specifications of L-ET1011C2-C-D

• Number Of Receivers: 1
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Lead Free Status / RoHS Status: Compliant

Gigabit Ethernet Transceiver
Hardware Interfaces
Table 9. Management Interface
1. PHYAD description applies to the 84-MLCC only. For the 68-MLCC, the valid range will be 0—15.
Management Interrupt
The ET1011C is capable of generating hardware interrupts on pin MDINT_N in response to a variety of user-selectable condi-
tions. MDINT_N is an open-drain, active-low signal that can be wire-ORed with several other ET1011C devices. A single 2.2
kΩ pull-up resistor is recommended for this wire-OR configuration.
When an interrupt occurs, the system can poll the status of the interrupt status register on each device to determine the origin
of the interrupt. There are nine conditions that can be selected to generate an interrupt:
The ET1011C is configured to generate an interrupt based on any of these conditions by use of the interrupt mask register (MII
register 24). By setting the corresponding bit in the interrupt mask register for the desired condition, the ET1011C will gener-
ate the desired interrupt. The ET1011C can be polled on the status of an activated interrupt condition by accessing MII register
interrupt status register (MII register 25). If this condition has occurred, the corresponding bit in the interrupt status register
will be set. The interrupt status register is self-clearing on a read operation.
28
MDINT_N
Pin Name
n
n
n
PHYAD
MDIO
Autonegotiation status change
Autonegotiation page received
FIFO overflow/underflow
MDC
[4:0]
67, 68, 69,
128-Pin
TQFP
70, 71
Pin #
90
91
89
40, 41, 42,
MLCC
84-Pin
43, 44
Pin #
(continued)
55
54
53
(PHYAD
MLCC
68-Pin
34, 35,
36, 37
Pin #
[3:0])
48
47
46
n
n
n
Interface Clock
PHY Address The physical address of the ET1011C is configured at reset
Management
Management
Management
Description
Link status change
CRC errors
Full error counter
Interface
Data I/O
Interrupt
Pin
by the current state of the PHYAD[4:0] pins. Once these pins
have been latched in at reset, the ET1011C is accessible via
the management interface at the configured address. The
default address is set to 1 by internal pull-up/downs. These
may be overridden by external pull-up/downs. The valid
range is 0 to 31
The management data clock (MDC) is a reference for the
data signal and is generated by the MAC. It can be turned off
when the MI is not being used. This pin has an internal pull-
down resistor. MDC is nominally
2.5 MHz, and can work up to a maximum of 12.5 MHz.
The management data input/output (MDIO) is a bidirectional
data signal between the MAC and one or more PHYs. MDIO
is a 3-state pin that allows either the MAC or the selected
PHY to drive this signal. This pin has an internal pull-up
resistor. An external pull-up resistor should also be used, the
exact value depending on the number of PHYs sharing the
MDIO signal. Data signals written by the MAC are sampled
by the PHY synchronously with respect to the MDC. Data
signals written by the PHY are generated synchronously with
respect to the MDC.
This pin requires an external pull-up (1 kΩ to 10 kΩ).
This pin is active-low and indicates an unmasked manage-
ment interrupt. This pin requires an external pull-up resistor
(1 kΩ to 4.7 kΩ). Pin is open drain.
1
.
n
n
n
Functional Description
Local/remote rx status change
Automatic speed downshift occurred
MDIO synchronization lost
September 2007
LSI Corporation