LAN8187I-JT Standard Microsystems (SMSC), LAN8187I-JT Datasheet - Page 52

• Manufacturer Part Number: LAN8187I-JT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN8187I-JT

• Number Of Receivers: 1
• Data Rate: 10/100Mbps
• Operating Supply Voltage (typ): 3.3V
• Package Type: TQFP
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Mounting: Surface Mount
• Pin Count: 64
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant

Revision 1.6 (02-27-09)
5.4.7
5.4.8
5.4.8.1
Power-Down reset: Automatically activated when the PHY comes out of power-down mode. The
internal power-down reset is extended by 256µs after exiting the power-down mode to allow the PLLs
to stabilize before the logic is released from reset.
These 3 reset sources are combined together in the digital block to create the internal “general reset”,
SYSRST, which is an asynchronous reset and is active HIGH. This SYSRST directly drives the PCS,
DSP and MII blocks. It is also input to the Central Bias block in order to generate a short reset for the
PLLs.
The SMI mechanism and registers are reset only by the Hardware and Software resets. During Power-
Down, the SMI registers are not reset. Note that some SMI register bits are not cleared by Software
reset – these are marked “NASR” in the register tables.
For several microseconds after coming out of reset, the MII will run at 2.5 MHz. After that it will switch
to 25 MHz if auto-negotiation is enabled.
LED Description
The PHY provides four LED signals. These provide a convenient means to determine the mode of
operation of the Phy. All LED signals are either active high or active low.
The four LED signals can be either active-high or active-low. Polarity depends upon the Phy address
latched in on reset. The LAN8187/LAN8187i senses each Phy address bit and changes the polarity of
the LED signal accordingly. If the address bit is set as level “1”, the LED polarity will be set to an active-
low. If the address bit is set as level “0”, the LED polarity will be set to an active-high.
The ACTIVITY LED output is driven active when CRS is active (high). When CRS becomes inactive,
the Activity LED output is extended by 128ms.
The LINK LED output is driven active whenever the PHY detects a valid link. The use of the 10Mbps
or 100Mbps link test status is determined by the condition of the internally determined speed selection.
The SPEED100 LED output is driven active when the operating speed is 100Mbit/s or during Auto-
negotiation. This LED will go inactive when the operating speed is 10Mbit/s or during line isolation
(register 31 bit 5).
The Full-Duplex LED output is driven active low when the link is operating in Full-Duplex mode.
Loopback Operation
The LAN8187/LAN8187i may be configured for near-end loopback and far loopback.
Near-end Loopback
Near-end loopback is a mode that sends the digital transmit data back out the receive data signals for
testing purposes as indicated by the blue arrows in
by setting bit register 0 bit 14 to logic one.
A large percentage of the digital circuitry is operational near-end loopback mode, because data is
routed through the PCS and PMA layers into the PMD sublayer before it is looped back. The COL
±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR
DATASHEET
52
Figure
5.2.The near-end loopback mode is enabled
SMSC LAN8187/LAN8187i
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