LAN8187I-JT Standard Microsystems (SMSC), LAN8187I-JT Datasheet
LAN8187I-JT
Specifications of LAN8187I-JT
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LAN8187I-JT Summary of contents
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... IEEE 802.3-2005 compliant register functions Integrated DSP with Adaptive Equalizer Baseline Wander (BLW) Correction LAN8187-JT for 64-pin, TQFP Lead-Free RoHS Compliant Package LAN8187i-JT for (Industrial Temp) 64-pin, TQFP Lead-Free RoHS Compliant Package SMSC LAN8187/LAN8187i LAN8187/LAN8187i ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & ...
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... Internal +1.8V Regulator Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.9.1 Disable the Internal +1.8V Regulator 4.9.2 Enable the Internal +1.8V Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.10 (TX_ER/TXD4)/nINT Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Revision 1.6 (02-27-09) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR 2 DATASHEET ® Technology Datasheet SMSC LAN8187/LAN8187i ...
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... Maximum Guaranteed Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.1.2 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.1.3 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.1.4 DC Characteristics - Input and Output Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Chapter 8 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.1 Magnetics Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.2 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.3 Reference Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.4 Evaluation board Chapter 9 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 SMSC LAN8187/LAN8187i ® Technology 3 DATASHEET Revision 1.6 (02-27-09) ...
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... List of Figures Figure 1.1 LAN8187/LAN8187i System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 1.2 LAN8187/LAN8187i Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2.1 Package Pinout (Top View Figure 4.1 100Base-TX Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 4.2 Receive Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 4.3 Relationship Between Received Data and specific MII Signals . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 4.4 Direct cable connection vs. Cross-over cable connection Figure 4.5 PHY Address Strapping on LED’ ...
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... ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR Datasheet List of Tables Table 2.1 LAN8187/LAN8187i 64-PIN TQFP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 3.1 MII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3.2 LED Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3.3 Management Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3.4 Boot Strap Configuration Inputs Table 3.5 General Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 3 ...
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... Table 6.8 10M RMII Receive Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 6.9 10M RMII Transmit Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 6.10 RMII CLKIN (REF_CLK) Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 6.11 Reset Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 6.12 LAN8187/LAN8187i Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 7.1 Maximum Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 7.2 ESD and LATCH-UP Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 7.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 7 ...
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... RMII requires only 6 pins for each MAC to PHY interface plus one common reference clock. The MII requires 16 pins for each MAC to PHY interface. The SMSC LAN8187/LAN8187i is capable of running in RMII mode. Please contact your SMSC sales representative for the latest RMII specification. ...
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... RXD[0..3] RX_DV Receive Section RX_ER RX_CLK 10M Rx CRS Logic COL/CRS_DV MDC MDIO Figure 1.2 LAN8187/LAN8187i Architectural Overview Revision 1.6 (02-27-09) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR 10M Tx 10M Logic Transmitter Transmit Section 100M Tx 100M Logic Transmitter ...
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... MODE2 NC VSS1 VSS7 NC VSS8 VSS7 NC VSS8 NC NC VDD33 NC VDD_CORE VDD33 VSS2 VDD_CORE SPEED100/PHYAD0 16 VSS2 SPEED100/PHYAD0 16 SMSC LAN8187/LAN8187i ® Technology LAN8187/LAN8187I LAN8187/LAN8187I LAN8187/LAN8187i Figure 2.1 Package Pinout (Top View) 9 DATASHEET 48 CRS COL/CRS_DV 48 CRS nINT/TX_ER/TXD4 COL/CRS_DV TXD3 nINT/TX_ER/TXD4 TXD2 TXD3 VDDIO TXD2 TXD1 ...
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... Table 2.1 LAN8187/LAN8187i 64-PIN TQFP Pinout PIN NO. PIN NAME 1 GPO0/RMII 2 GPO1/PHYAD4 3 GPO2 4 MODE0 5 MODE1 6 MODE2 7 VSS1 VSS7 10 VSS8 VDD33 14 VDD_CORE 15 VSS2 16 SPEED100/PHYAD0 17 LINK/PHYAD1 ACTIVITY/PHYAD2 20 FDUPLEX/PHYAD3 XTAL2 23 CLKIN/XTAL1 24 VSS3 25 nRST 26 MDIO 27 MDC 28 VSS4 29 RXD3/nINTSEL 30 RXD2 31 RXD1 32 RXD0 Revision 1.6 (02-27-09) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR PIN NO ...
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... SIGNAL NAME TXD0 TXD1 TXD2 TXD3 nINT/ TX_ER/ TXD4 TX_EN TX_CLK SMSC LAN8187/LAN8187i ® Technology Table 3.1 MII Signals TYPE DESCRIPTION I Transmit Data 0: Bit 0 of the 4 data bits that are accepted by the PHY for transmission. I Transmit Data 1: Bit 1 of the 4 data bits that are accepted by the PHY for transmission ...
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... SFD byte (10101011) is received. In 10BT, half- duplex mode, transmitted data is not looped back onto the receive data pins, per the RMII standard. Note: See Section 4.6.3, "MII vs. RMII Configuration," on page 25 for more details. 12 DATASHEET ® Technology Datasheet SMSC LAN8187/LAN8187i ...
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... SIGNAL NAME GPO1/ PHYAD4 FDUPLEX/ PHYAD3 ACTIVITY/ PHYAD2 LINK/ PHYAD1 SPEED100/ PHYAD0 SMSC LAN8187/LAN8187i ® Technology Table 3.2 LED Signals TYPE DESCRIPTION O Carrier Sense: Indicates detection of carrier. O Receive Data Valid: Indicates that recovered and decoded data nibbles are being presented on RXD[3:0]. ...
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... Table 4.4, “Boot Strapping Configuration Resistors,” on page 32) to VDDIO to set the device in RMII mode. Note: See Section 4.6.3, "MII vs. RMII Configuration," on page 25 for more details. 14 DATASHEET ® Technology Datasheet a 54, for 54, for 54, for Table 4.3, “Auto-MDIX Control,” on Table 4.3, SMSC LAN8187/LAN8187i ...
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... CLKIN/XTAL1 XTAL2 GPO2 GPO1 GPO0/RMII SIGNAL NAME TXP TXN SMSC LAN8187/LAN8187i ® Technology Table 3.5 General Signals TYPE DESCRIPTION I/O LAN Interrupt – Active Low output. Place a pull-up external resistor (see Table 4.4, “Boot Strapping Configuration Resistors,” on page 32) to VCC 3 ...
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... ESR < 1ohm near this pin and connect the capacitor from this pin to ground. X5R or X7R ceramic capacitors are recommended since they exhibit an ESR lower than 0.1ohm at frequencies greater than 10kHz. +3.3V Digital Power POWER +1.6V to +3.6V Variable I/O Pad Power POWER Digital Ground (GND) POWER 16 DATASHEET ® Technology Datasheet SMSC LAN8187/LAN8187i ...
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... The first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles, 0 through F. The remaining code-groups are given letter designations with slashes on either side. For example, an IDLE code-group is /I/, a transmit error code-group is /H/, etc. SMSC LAN8187/LAN8187i ® Technology ...
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... Sent for falling TX_EN Sent for falling TX_EN Sent for rising TX_ER INVALID INVALID INVALID INVALID 18 DATASHEET ® Technology Datasheet TRANSMITTER INTERPRETATION 0 0000 DATA 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 SMSC LAN8187/LAN8187i ...
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... Phase Lock Loop (PLL) The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz logic and the 100Base-Tx Transmitter. SMSC LAN8187/LAN8187i ® Technology Table 4.1 4B/5B Code Table (continued) RECEIVER ...
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... Mbps Serial DSP: Timing MLT-3 recovery, Equalizer and BLW Correction RJ45 MLT-3 MLT-3 6 bit Data Figure 4.2 Receive Data Path Figure 4.2. Detailed descriptions are given below. 20 DATASHEET ® Technology Datasheet Descrambler 25MHz by 5 bits and SIPO CAT-5 SMSC LAN8187/LAN8187i ...
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... SIGDET becomes false. RX_DV is asserted when the first nibble of translated /J/K/ is ready for transfer over the Media Independent Interface (MII CLEAR-TEXT RX_CLK RX_DV RXD Figure 4.3 Relationship Between Received Data and specific MII Signals SMSC LAN8187/LAN8187i ® Technology data data data data 5 5 ...
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... Detect," on page For RMII, TXD[1:0] shall transition synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted for transmission by the LAN8187/LAN8187i. TXD[1:0] shall be “00” to indicate idle when TX_EN is deasserted. Values of TXD[1:0] other than “00” when TX_EN is deasserted are reserved for out-of-band signalling (to be defined). Values other than “ ...
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... For MII, the 4 bit data nibbles are sent to the MII block. In MII mode, these data nibbles are valid on the rising edge of the 2.5 MHz RX_CLK. For RMII, the 2bit data nibbles are sent to the RMII block. In RMII mode, these data nibbles are valid on the rising edge of the RMII REF_CLK. SMSC LAN8187/LAN8187i ® Technology 23 DATASHEET Revision 1 ...
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... RMII The SMSC LAN8187/LAN8187i supports the low pin count Reduced Media Independent Interface (RMII) intended for use between Ethernet PHYs and Switch ASICs. Under IEEE 802.3, an MII comprised of 16 pins for data and control is defined. In devices incorporating many MACs or PHY interfaces such as switches, the number of pins can add significant cost as the port counts increase ...
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... MII vs. RMII Configuration The LAN8187/LAN8187i must be configured to support the MII or RMII bus for connectivity to the MAC. This configuration is done through the GPO0/RMII pin. To select MII mode, float the GPO0/RMII pin. To select RMII mode, pull-high with an external resistor (see Resistors,” ...
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... RX_ER/ RXD4/ COL RXD0 RXD1 TXD2 TXD3 TX_ER/ TXD4 CRS RX_DV RXD2 RXD3 TX_CLK RX_CLK CLKIN/XTAL1 26 DATASHEET ® Technology Datasheet Mapping", shown below, RMII MODE TXD0 TXD1 TX_EN RX_ER Note 4.2 CRS_DV RXD0 RXD1 Note 4.1 Note 4.1 REF_CLK SMSC LAN8187/LAN8187i ...
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... Writing register 4 bits [8:5] allows software control of the capabilities advertised by the PHY. Writing register 4 does not automatically re-start auto-negotiation. Register 0, bit 9 must be set before the new abilities will be advertised. Auto-negotiation can also be disabled via software by clearing register 0, bit 12. The LAN8187/LAN8187i does not support “Next Page” capability. SMSC LAN8187/LAN8187i ® Technology ...
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... Parallel Detection If the LAN8187/LAN8187i is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is presumed to be Half Duplex per the IEEE standard. ...
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... The table below shows how the control pins and the register are used to configure the Auto-MDIX function. REGISTER 27 BITS AMDIXEN Note either Note Dont Care. SMSC LAN8187/LAN8187i ® Technology Table 4.3 Auto-MDIX Control EXTERNAL PINS CH_SELECT DATASHEET STATUS TX AND RX OUTPUT PINS Auto-MDIX Normal MDI Crossed MDIX Auto-MDIX Normal MDI Crossed MDIX Revision 1 ...
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... ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR 32) is attached from REG_EN to VSS. When both VDDIO and VDDA Section 4.9.2, when the REG_EN pin is left Table 4.4, “Boot Strapping Configuration 30 DATASHEET ® Technology Datasheet Table 4.4, “Boot Strapping SMSC LAN8187/LAN8187i ...
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... Variable Voltage I/O The Digital I/O pins on the LAN8187/LAN8187i are variable voltage to take advantage of low power savings from shrinking technologies. These pins can operate from a low I/O voltage of +1. +3.6V. Due to this low voltage feature addition, the system designer needs to take consideration as for two aspects of their design ...
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... Interrupt 4.13.1 Serial Management Interface (SMI) The Serial Management Interface is used to control the LAN8187/LAN8187i and obtain its status. This interface supports registers 0 through 6 as required by Clause 22 of the 802.3 standard, as well as “vendor-specific” registers allowed by the specification. Non-supported registers (7 to 15) will be read as hexadecimal “ ...
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... Figure 4.6 MDIO Timing and Frame Structure - READ Cycle MDC MDIO 32 1 Start of OP Preamble Frame Code Figure 4.7 MDIO Timing and Frame Structure - WRITE Cycle SMSC LAN8187/LAN8187i ® Technology Read Cycle PHY Address Register Address Data To Phy Write Cycle PHY Address Register Address Data To Phy 33 DATASHEET ...
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Chapter 5 Registers Reset Loopback Speed Select A/N Enable 100Base- 100Base-TX 100Base-TX 10Base-T T4 Full Duplex Half Duplex Full Duplex PHY ID Number (Bits 3-18 of the Organizationally ...
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Table 5.6 Auto-Negotiation Link Partner Base Page Ability Register: Register 5 (Extended Next Acknowledge Remote Reserved Page Fault Table 5.7 Auto-Negotiation Expansion Register: Register 6 (Extended Reserved Table 5.8 ...
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Table 5.11 Register 10 (Extended ...
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Reserved RSVD EDPWRDOWN RSVD LOWSQEN RSVD = Reserved Reserved MIIMODE Table 5.17 Silicon Revision Register 16: Vendor-Specific ...
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Table 5.24 Special Control/Status Indications Register 27: Vendor-Specific AMDIXCTRL Reserved CH_SELECT Table 5.25 Special Internal Testability Control Register 28: Vendor-Specific Table 5.26 ...
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Table 5.28 PHY Special Control/Status Register 31: Vendor-Specific Reserved Autodone Reserved GPO2 GPO1 GPO0 Enable 4B5B Reserved Speed Indication Reserved Scramble Disable 0 ...
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... ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR Table 5.29 SMI Register Mapping DESCRIPTION 40 DATASHEET ® Technology Datasheet Group Basic Basic Extended Extended Extended Extended Extended Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific Vendor-specific SMSC LAN8187/LAN8187i ...
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... Duplex 1.10:6 Reserved 1.5 Auto-Negotiate 1 = auto-negotiate process completed 0 = auto-negotiate process not completed Complete SMSC LAN8187/LAN8187i ® Technology Table 5.30 Register 0 - Basic Control DESCRIPTION when setting this bit do not set other bits in this register. The configuration (as described in Section 5.4.9.2) is set from the register bit values, and not from the mode pins ...
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... No PAUSE 01 = Symmetric PAUSE 10 = Asymmetric PAUSE toward link partner 11 = Both Symmetric PAUSE and Asymmetric PAUSE toward local device 42 DATASHEET ® Technology Datasheet MODE DEFAULT MODE DEFAULT RW 0007h MODE DEFAULT RW C0h RW 0Ch RW 4h MODE DEFAULT R/W 00 SMSC LAN8187/LAN8187i ...
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... Full Duplex 5.7 100Base-TX 5.6 10Base-T Full Duplex 5.5 10Base-T 5.4:0 Selector Field SMSC LAN8187/LAN8187i ® Technology DESCRIPTION able ability This Phy does not support 100Base-T4 with full duplex full duplex ability able ability 1 = 10Mbps with full duplex 10Mbps with full duplex ability ...
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... This bit is only active in RMII mode. In this mode the user needs to supply a 50MHz clock to the PHY. This mode works even if MII Isolate (0.10) is set. 44 DATASHEET ® Technology Datasheet MODE DEFAULT MODE DEFAULT 0001 RO 0 MODE DEFAULT SMSC LAN8187/LAN8187i ...
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... MODE 18.4:0 PHYAD Table 5.40 Register 26 - Symbol Error Counter ADDRESS NAME 26.15:0 Sym_Err_Cnt SMSC LAN8187/LAN8187i ® Technology DESCRIPTION Write as 0, ignore on read. Alternate Interrupt Mode Primary interrupt system enabled (Default Alternate interrupt system enabled. See Section 5.3, "Interrupt Management," on page Write as 0, ignore on read ...
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... Do not write to this register. Ignore on read. DESCRIPTION Ignore on read ENERGYON generated 0 = not source of interrupt 1 = Auto-Negotiation complete 0 = not source of interrupt 1 = Remote Fault Detected 0 = not source of interrupt 46 DATASHEET ® Technology Datasheet MODE DEFAULT RW, 0 NASR RW 000000 XXXXb MODE DEFAULT RW N/A MODE DEFAULT SMSC LAN8187/LAN8187i ...
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... Reserved 31.10 Reserved 31.9:7 GPO[2:0] 31.6 Enable 4B5B 31.5 Reserved 31.4:2 Speed Indication SMSC LAN8187/LAN8187i ® Technology DESCRIPTION 1 = Link Down (link status negated not source of interrupt 1 = Auto-Negotiation LP Acknowledge 0 = not source of interrupt 1 = Parallel Detection Fault 0 = not source of interrupt 1 = Auto-Negotiation Page Received 0 = not source of interrupt Ignore on read ...
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... Reading register 29 Falling 1.2 Reading register 1 or Reading register 29 Rising 5.14 Falling 5.14 or Read register 29 Rising 6.4 Falling 6.4 or Reading register 6, or Reading register 29 or Re-AutoNegotiate or Link down Rising 6.1 Falling of 6.1 or Reading register 6, or Reading register 29 Re-AutoNegotiate, or Link Down. SMSC LAN8187/LAN8187i ...
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... ENERGYON (17.1) goes active and nINT will be asserted low. To de-assert the nINT interrupt output, either. 1. Clear the ENERGYON bit (17.1), by removing the cable, then writing a ‘1’ to register 29. Clear the Mask bit 30.1 SMSC LAN8187/LAN8187i ® Technology Interrupt Source Event to Assert nINT 17 ...
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... Link Integrity Test The LAN8187/LAN8187i performs the link integrity test as outlined in the IEEE 802.3u (Clause 24-15) Link Monitor state diagram. The link status is multiplexed with the 10Mbps link status to form the reportable link status bit in Serial Management Register 1, and is driven to the LINK LED. ...
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... When 17.13 is low, energy detect power-down is disabled. 5.4.6 Reset The LAN8187/LAN8187i has 3 reset sources: Hardware reset (HWRST): connected to the nRST input. At power up, nRST must not go high until after the VDDIO and VDD_CORE supplies are stable, as shown in To initiate a hardware reset, nRST must be held LOW for at least 100 us to ensure that the Phy is properly reset, as shown in During a Hardware reset, an external clock must be supplied to the CLKIN signal ...
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... The four LED signals can be either active-high or active-low. Polarity depends upon the Phy address latched in on reset. The LAN8187/LAN8187i senses each Phy address bit and changes the polarity of the LED signal accordingly. If the address bit is set as level “1”, the LED polarity will be set to an active- low. If the address bit is set as level “ ...
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... Far-end system TXD 10/100 X Ethernet RXD MAC X Digital Ethernet Transceiver Figure 5.3 Far Loopback Block Diagram 5.4.8.3 Connector Loopback The LAN8187/LAN8187i maintains reliable transmission over very short cables, and can be tested in a connector loopback as shown in SMSC LAN8187/LAN8187i ® Technology Analog SMSC TX XFMR ...
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... SMSC Table 5.48 MODE[2:0] Bus DEFAULT REGISTER BIT VALUES REGISTER 0 54 DATASHEET ® Technology Datasheet RJ45 Loopback Cable. Created by connecting pin 1 to pin 3 and connecting pin 2 to pin 6. REGISTER 4 [13,12,10,8] [8,7,6,5] 0000 N/A 0001 N/A 1000 N/A 1001 N/A SMSC LAN8187/LAN8187i ...
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... MODE[2:0] bits are set to this mode. To exit this mode, the MODE[2:0] bits must be configured to some other value and a soft reset must be issued. 111 All capable. Auto-negotiation enabled. SMSC LAN8187/LAN8187i ® Technology Table 5.48 MODE[2:0] Bus (continued) 55 DATASHEET DEFAULT REGISTER BIT VALUES ...
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... Chapter 6 AC Electrical Characteristics The timing diagrams and limits in this section define the requirements placed on the external signals of the LAN8187/LAN8187i. 6.1 Serial Management Interface (SMI) Timing The Serial Management Interface is used for status and control as described in Clock - MDC Data Out - MDIO ...
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... Figure 6.2 100M MII Receive Timing Diagram Table 6.2 100M MII Receive Timing Values PARAMETER DESCRIPTION T2.1 Receive signals setup to RX_CLK rising T2.2 Receive signals hold from RX_CLK rising RX_CLK frequency RX_CLK Duty-Cycle SMSC LAN8187/LAN8187i ® Technology T 2.1 2.2 Valid Data MIN TYP ...
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... Transmit signals required hold after TX_CLK rising TX_CLK frequency TX_CLK Duty-Cycle Revision 1.6 (02-27-09) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR T 3.1 Valid Data MIN TYP MAX DATASHEET ® Technology Datasheet UNITS NOTES ns ns MHz % SMSC LAN8187/LAN8187i ...
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... Figure 6.4 10M MII Receive Timing Diagram Table 6.4 10M MII Receive Timing Values PARAMETER DESCRIPTION T4.1 Receive signals setup to RX_CLK rising T4.2 Receive signals hold from RX_CLK rising RX_CLK frequency RX_CLK Duty-Cycle SMSC LAN8187/LAN8187i ® Technology T T 4.1 4.2 Valid Data MIN TYP ...
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... Figure 6.6 100M RMII Receive Timing Diagram Revision 1.6 (02-27-09) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR T 5.1 Valid Data MIN TYP MAX 6.1 Valid Data 60 DATASHEET ® Technology Datasheet UNITS NOTES ns ns MHz % SMSC LAN8187/LAN8187i ...
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... Figure 6.7 100M RMII Transmit Timing Diagram Table 6.7 100M RMII Transmit Timing Values PARAMETER DESCRIPTION T8.1 Transmit signals required setup to rising edge of CLKIN T8.2 Transmit signals required hold after rising edge of REF_CLK CLKIN frequency SMSC LAN8187/LAN8187i ® Technology MIN TYP MAX ...
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... Output delay from rising edge of CLKIN to receive signals output valid CLKIN frequency Revision 1.6 (02-27-09) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR T 9.1 Valid Data MIN TYP MAX DATASHEET ® Technology Datasheet UNITS NOTES ns MHz SMSC LAN8187/LAN8187i ...
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... REF_CLK CLKIN frequency 6.4 RMII CLKIN Timing Table 6.10 RMII CLKIN (REF_CLK) Timing Values PARAMETER DESCRIPTION CLKIN frequency CLKIN Frequency Drift CLKIN Duty Cycle CLKIN Jitter SMSC LAN8187/LAN8187i ® Technology T T 10.1 10.2 Valid Data MIN TYP MAX ...
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... ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR T 11 11.2 11.3 T 11.4 Figure 6.10 Reset Timing Diagram Table 6.11 Reset Timing Values MIN TYP MAX 100 200 10 20 800 64 DATASHEET ® Technology Datasheet UNITS NOTES clock cycles for 25 MHz clock or 40 clock cycles for 50MHz clock SMSC LAN8187/LAN8187i ...
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... Datasheet 6.6 Clock Circuit LAN8187/LAN8187i can accept either a 25MHz crystal or a 25MHz single-ended clock oscillator (±50ppm) input for operation in MII mode. If the single-ended clock oscillator method is implemented, XTAL2 should be left unconnected and XTAL1/CLKIN should be driven with a nominal 0-3.3V clock signal. The user is required to supply a 50MHz single-ended clock for RMII operation. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum ...
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... PARAMETER CONDITIONS Power pins to all other pins. VDD33,VDDIO To VSS ground Digital IO VSS to all other pins VSS LAN8187-JT Operating Temperature LAN8187i-JT Operating Temperature Storage Temperature Table 7.2 ESD and LATCH-UP Performance PARAMETER CONDITIONS ESD PERFORMANCE Human Body Model All Pins EN61000-4-2 Contact ...
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... Table 7.3 Recommended Operating Conditions PARAMETER CONDITIONS VDD33 to VSS VDD33 INPUT VOLTAGE ON DIGITAL PINS VOLTAGE ON ANALOG I/O PINS (RXP, RXN) T LAN8187-JT A AMBIENT TEMPERATURE T LAN8187I- A AEZG SMSC LAN8187/LAN8187i ® Technology MIN TYP MAX UNITS 3.0 3.3 3.6 V 0.0 VDDI V O 0.0 +3.6 V ...
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... Note 7.1 1.1 39 128.7 0.9 37 122.1 0.1 34.1 83.88 Note 7.1 0.5 13.85 45.7 0.4 13.0 42.9 0.3 12.4 37.02 Note 7.1 0.39 3.52 11.62 0.34 3.07 10.13 0.3 2.44 4.45 Note 7.1 SMSC LAN8187/LAN8187i ...
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... VDDIO – +0.4 V TX_EN VDDIO – +0.4 V TX_CLK RXD0 RXD1 RXD2 RXD3 RX_ER/RXD4 RX_DV RX_CLK CRS COL MDC VDDIO – +0.4 V MDIO VDDIO – +0.4 V nINT/TX_ER/TXD4 VDDIO – +0.4 V SMSC LAN8187/LAN8187i ® Technology Table 7.5 MII Bus Interface Signals +0.5 V +0.5 V +0.5 V +0 ...
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... Table 7.13, 72 +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0 +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V 3.7 V +0.4 V VDDIO – +0.4 V SMSC LAN8187/LAN8187i ...
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... EXRES1 AI NC AI/O Table 7.11 Internal Pull-Up / Pull-Down Configurations NAME SPEED100/PHYAD0 LINK/PHYAD1 ACTIVITY/PHYAD2 FDUPLEX//PHYAD3 GPO1/PHYAD4 MODE0 MODE1 MODE2 nINT/TX_ER/TXD4 nRST RXD3/nINTSEL MDIO MDC RX_ER/RXD4 RX_DV GPO0/RMII SMSC LAN8187/LAN8187i ® Technology Table 7.9 General Signals +0 Table 7.10 Analog References V V ...
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... RFS 1.4 SYMBOL MIN TYP V 2.2 2.5 OUT V 300 420 DS 72 DATASHEET ® Technology Datasheet UNITS NOTES mVpk Note 7.4 mVpk Note 7.4 % Note 7.4 nS Note 7.4 nS Note 7 Note 7 Note 7.6 MAX UNITS NOTES 2.8 V Note 7.7 585 mV SMSC LAN8187/LAN8187i ...
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... SOIC for user configurable Magnetics On board LED indicators for Speed 100 Full Duplex RJ-45 Connector LEDs for Link and Activity Interfaces Through 40-pin Connector as Defined in the MII Specification Powered by 5.0V from the 40-Pin MII Connector SMSC LAN8187/LAN8187i ® Technology 73 DATASHEET Revision 1.6 (02-27-09) ...
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... Support testing of FPGA implementations of MAC Assist inter operability test of various networks Verify MII compliance Verify performance of HP AutoMDIX feature Verify Variable IO compliance Revision 1.6 (02-27-09) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR 74 DATASHEET ® Technology Datasheet SMSC LAN8187/LAN8187i ...
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... Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm per side. 4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5. Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC LAN8187/LAN8187i ® Technology MAX REMARKS 1 ...