LAN8187I-JT Standard Microsystems (SMSC), LAN8187I-JT Datasheet - Page 51

• Manufacturer Part Number: LAN8187I-JT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN8187I-JT

• Number Of Receivers: 1
• Data Rate: 10/100Mbps
• Operating Supply Voltage (typ): 3.3V
• Package Type: TQFP
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Mounting: Surface Mount
• Pin Count: 64
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant

±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR
Datasheet
SMSC LAN8187/LAN8187i
5.4.5
5.4.5.1
5.4.5.2
5.4.6
Power-Down modes
There are 2 power-down modes for the Phy:
General Power-Down
This power-down is controlled by register 0, bit 11. In this mode the entire PHY, except the
management interface, is powered-down and stays in that condition as long as bit 0.11 is HIGH. When
bit 0.11 is cleared, the PHY powers up and is automatically reset.
Energy Detect Power-Down
This power-down mode is activated by setting bit 17.13 to 1. In this mode when no energy is present
on the line the PHY is powered down, except for the management interface, the SQUELCH circuit and
the ENERGYON logic. The ENERGYON logic is used to detect the presence of valid energy from
100Base-TX, 10Base-T, or Auto-negotiation signals
In this mode, when the ENERGYON signal is low, the PHY is powered-down, and nothing is
transmitted. When energy is received - link pulses or packets - the ENERGYON signal goes high, and
the PHY powers-up. It automatically resets itself into the state it had prior to power-down, and asserts
the nINT interrupt if the ENERGYON interrupt is enabled.
to activate ENERGYON may be lost.
When 17.13 is low, energy detect power-down is disabled.
Reset
The LAN8187/LAN8187i has 3 reset sources:
Hardware reset (HWRST): connected to the nRST input. At power up, nRST must not go high until
after the VDDIO and VDD_CORE supplies are stable, as shown in
To initiate a hardware reset, nRST must be held LOW for at least 100 us to ensure that the Phy is
properly reset, as shown in
During a Hardware reset, an external clock must be supplied to the CLKIN signal.
Software (SW) reset: Activated by writing register 0, bit 15 high. This signal is self- clearing. After the
register-write, internal logic extends the reset by 256µs to allow PLL-stabilization before releasing the
logic from reset.
The IEEE 802.3u standard, clause 22 (22.2.4.1.1) states that the reset process should be completed
within 0.5s from the setting of this bit.
VDD33 Starts
3.3V
1.8V
0V
Figure 5.1 Reset Timing Diagram
VDD_CORE Starts
Figure
DATASHEET
6.10.
51
®
Technology
nRST Released
The first and possibly the second packet
Figure
5.1.
Revision 1.6 (02-27-09)