LAN8700IC-AEZG Standard Microsystems (SMSC), LAN8700IC-AEZG Datasheet - Page 41

• Manufacturer Part Number: LAN8700IC-AEZG
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN8700IC-AEZG

• Number Of Receivers: 1
• Data Rate: 10/100Mbps
• Operating Supply Voltage (typ): 3.3V
• Package Type: QFN EP
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant

±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR
Datasheet
SMSC LAN8700/LAN8700i
ADDRESS
ADDRESS
1.10:6
0.6:0
0.15
0.14
0.13
0.12
0.11
0.10
1.15
1.14
1.13
1.12
1.11
0.9
0.8
0.7
1.5
100Base-TX Half
100Base-TX Full
Auto-Negotiate
Speed Select
Restart Auto-
Duplex Mode
Collision Test
10Base-T Half
Power Down
10Base-T Full
Negotiation
100Base-T4
Loopback
Negotiate
Reserved
Reserved
Complete
Enable
NAME
Isolate
Reset
Duplex
Duplex
Duplex
Duplex
Auto-
NAME
1 = software reset. Bit is self-clearing. For best results,
1 = loopback mode,
0 = normal operation
1 = 100Mbps,
0 = 10Mbps.
Ignored if Auto Negotiation is enabled (0.12 = 1).
1 = enable auto-negotiate process
0 = disable auto-negotiate process
1 = General power down mode,
0 = normal operation
1 = electrical isolation of PHY from MII
0 = normal operation
1 = restart auto-negotiate process
0 = normal operation. Bit is self-clearing.
1 = Full duplex,
0 = Half duplex.
1 = enable COL test,
0 = disable COL test
Ignored if Auto Negotiation is enabled (0.12 = 1).
1 = T4 able,
0 = no T4 ability
1 = TX with full duplex,
0 = no TX full duplex ability
1 = TX with half duplex,
0 = no TX half duplex ability
1 = 10Mbps with full duplex
0 = no 10Mbps with full duplex ability
1 = 10Mbps with half duplex
0 = no 10Mbps with half duplex ability
1 = auto-negotiate process completed
0 = auto-negotiate process not completed
Table 5.30 Register 0 - Basic Control
when setting this bit do not set other bits in this
register. The configuration (as described in
Section
and not from the mode pins.
(overrides 0.13 and 0.8)
Table 5.31 Register 1 - Basic Status
5.4.9.2) is set from the register bit values,
DATASHEET
DESCRIPTION
DESCRIPTION
®
41
Technology in a Small Footprint
MODE
MODE
RW/
RW/
RW
RW
RW
RW
RW
RW
RW
RO
SC
SC
Revision 2.2 (12-04-09)
RO
RO
RO
RO
RO
RO
MODE[2:0]
MODE[2:0]
MODE[2:0]
DEFAULT
DEFAULT
Set by
Set by
Set by
bus
bus
bus
0
0
0
0
0
0
0
0
1
1
1
1
0