LAN8700IC-AEZG Standard Microsystems (SMSC), LAN8700IC-AEZG Datasheet
LAN8700IC-AEZG
Specifications of LAN8700IC-AEZG
Available stocks
Related parts for LAN8700IC-AEZG
LAN8700IC-AEZG Summary of contents
Page 1
PRODUCT FEATURES Single-Chip Ethernet Physical Layer Transceiver (PHY) ESD Protection levels of ±8kV HBM without external protection devices ESD protection levels of EN/IEC61000-4-2, ±8kV contact mode, and ±15kV for air discharge mode per independent test facility ® Comprehensive flexPWR Technology ...
Page 2
... LAN8700C-AEZG for 36-pin, QFN lead-free RoHS compliant package LAN8700iC-AEZG for (Industrial Temp) 36-pin, QFN lead-free RoHS compliant package LAN8700C-AEZG-TR for 36-pin, QFN lead-free RoHS compliant package (tape and reel) This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © ...
Page 3
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet Table of Contents Chapter 1 General Description . . . . . . . . . . . . . . . . . . . ...
Page 4
PHY Address Strapping and LED Output Polarity Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.12 ...
Page 5
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet List of Figures Figure 1.1 LAN8700/LAN8700i System Block Diagram . . . . . . . . . . . . . . . . . ...
Page 6
List of Tables Table 2.1 LAN8700/LAN8700i 36-PIN QFN Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 7
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet Table 5.42 Register 28 - Special Internal Testability Controls ...
Page 8
Chapter 1 General Description The SMSC LAN8700/LAN8700i is a low-power, industrial temperature (LAN8700i), variable I/O voltage, analog interface IC with HP Auto-MDIX support for high-performance embedded Ethernet applications. The LAN8700/LAN8700i can be configured to operate on a single 3.3V supply ...
Page 9
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet MODE0 Auto- MODE1 MODE Control Negotiation MODE2 Management nRST SMI Control MII TXD[0..3] TX_EN 100M Rx TX_ER Logic TX_CLK RXD[0..3] RX_DV Receive Section RX_ER RX_CLK 10M ...
Page 10
Chapter 2 Pin Configuration 2.1 Package Pin-out Diagram and Signal Table nINT/TX_ER/TXD4 MDC CRS/PHYAD4 MDIO nRST TX_EN VDD33 VDD_CORE SPEED100/PHYAD0 Revision 2.2 (12-04-09) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR LAN8700/LAN8700I ...
Page 11
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet Table 2.1 LAN8700/LAN8700i 36-PIN QFN Pinout PIN NO. PIN NAME 1 nINT/TX_ER/TXD4 2 MDC 3 CRS/PHYAD4 4 MDIO 5 nRST 6 TX_EN 7 VDD33 8 VDD_CORE ...
Page 12
Chapter 3 Pin Description This chapter describes the signals on each pin. When a lower case “n” is used at the beginning of the signal name, it indicates that the signal is active low. For example, nRST indicates that the ...
Page 13
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet SIGNAL NAME TX_CLK RXD0/ MODE0 RXD1/ MODE1 RXD2/ MODE2 RXD3/ nINTSEL SMSC LAN8700/LAN8700i ® Technology in a Small Footprint Table 3.1 MII Signals (continued) TYPE DESCRIPTION ...
Page 14
SIGNAL NAME RX_ER/ RXD4/ RX_DV RX_CLK/ REGOFF COL/ RMII/ CRS_DV CRS/ PHYAD4 SIGNAL NAME SPEED100/ PHYAD0 Revision 2.2 (12-04-09) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Table 3.1 MII Signals (continued) TYPE DESCRIPTION OPD ...
Page 15
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet LINK/ PHYAD1 ACTIVITY/ PHYAD2 FDUPLEX/ PHYAD3 SIGNAL NAME MDIO MDC Table 3.4 Boot Strap Configuration Inputs SIGNAL NAME CRS/ PHYAD4 FDUPLEX/ PHYAD3 ACTIVITY/ PHYAD2 LINK/ PHYAD1 ...
Page 16
Table 3.4 Boot Strap Configuration Inputs SIGNAL NAME COL/ RMII/ CRS_DV RXD3/ nINTSEL Note 3.1 On nRST transition high, the PHY latches the state of the configuration pins in this table. SIGNAL NAME nINT/ TX_ER/ TXD4 nRST CLKIN/ XTAL1 XTAL2 ...
Page 17
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet SIGNAL NAME TXP TXN RXP RXN SIGNAL NAME EXRES1 SIGNAL NAME VDDIO VDD33 VDDA3.3 VDD_CORE VSS SMSC LAN8700/LAN8700i ® Technology in a Small Footprint Table 3.6 ...
Page 18
Chapter 4 Architecture Details 4.1 Top Level Functional Architecture Functionally, the PHY can be divided into the following sections: 100Base-TX transmit and receive 10Base-T transmit and receive MII or RMII interface to the controller Auto-negotiation to automatically determine the best ...
Page 19
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet The first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles, 0 through F. The remaining code-groups are given letter designations ...
Page 20
CODE GROUP SYM 00000 V INVALID, RX_ER if during RX_DV 00001 V INVALID, RX_ER if during RX_DV 00010 V INVALID, RX_ER if during RX_DV 00011 V INVALID, RX_ER if during RX_DV 00101 V INVALID, RX_ER if during RX_DV 01000 V ...
Page 21
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet RX_CLK (for MII only) MAC Ext Ref_CLK (for RMII only) MII 25Mhz by 4 bits or RMII 50Mhz by 2 bits MLT-3 NRZI NRZI Converter Converter ...
Page 22
Descrambling The descrambler performs an inverse function to the scrambler in the transmitter and also performs the Serial In Parallel Out (SIPO) conversion of the data. During reception of IDLE (/I/) symbols. the descrambler synchronizes its descrambler key to ...
Page 23
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet 4.3.8 Receiver Errors During a frame, unexpected code-groups are considered receive errors. Expected code groups are the DATA set (0 through F), and the /T/R/ (ESD) ...
Page 24
Manchester Encoding The 4-bit wide data is sent to the TX10M block. The nibbles are converted to a 10Mbps serial NRZI data stream. The 10M PLL locks onto the external clock or internal oscillator and produces a 20MHz clock. ...
Page 25
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet 4.5.4 Jabber Detection Jabber is a condition in which a station transmits for a period of time longer than the maximum permissible packet length, usually due ...
Page 26
The RMII includes 6 interface signals with one of the signals being optional: transmit data - TXD[1:0] transmit strobe - TX_EN receive data - RXD[1:0] receive error - RX_ER (Optional) carrier sense - CRS_DV Reference Clock - CLKIN/XTAL1 (RMII references ...
Page 27
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet Most of the MII and RMII pins are multiplexed. describes the relationship of the related device pins to what pins are used in MII and RMII ...
Page 28
The advertised capabilities of the PHY are stored in register 4 of the SMI registers. The default advertised by the PHY is determined by user-defined on-chip signal options. The following blocks are activated during an Auto-negotiation session: Auto-negotiation (digital) 100M ...
Page 29
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet abilities will be advertised. Auto-negotiation can also be disabled via software by clearing register 0, bit 12. The LAN8700/LAN8700i does not support “Next Page” capability. 4.7.1 ...
Page 30
The Auto-MDIX function can be disabled through an internal register. Figure 4.4 Direct Cable Connection vs. Cross-over Cable Connection. 4.9 Internal +1.8V Regulator Disable One feature of the flexPWR technology is the ability to configure the internal 1.8V regulator off. ...
Page 31
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet 4.10 nINT/TX_ER/TXD4 Strapping The nINT, TX_ER, and TXD4 functions share a common pin. There are two functional modes for this pin, the TX_ER/TXD4 mode and nINT ...
Page 32
Table 4.3 Boot Strapping Configuration Resistors I/O voltage 3.0 to 3.6 2.0 to 3.0 1.6 to 2.0 4.12.2 I/O Voltage Stability The I/O voltage the System Designer applies on VDDIO needs to maintain its value with a tolerance of ...
Page 33
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet MDC MDI0 32 1 Start of OP Preamble Frame Code Figure 4.6 MDIO Timing and Frame Structure - READ Cycle MDC MDIO ...
Page 34
Chapter 5 Registers Reset Loopback Speed A/N Select Enable 100Base 100Base 100Base 10Base- T -T4 -TX -TX Full Half Full Duplex Duplex Duplex PHY ID Number (Bits ...
Page 35
Table 5.5 Auto-Negotiation Advertisement: Register 4 (Extended Next Reserved Remote Reserved Page Fault Table 5.6 Auto-Negotiation Link Partner Base Page Ability Register: Register 5 (Extended Next Acknowledge Remote Reserved Page Fault ...
Page 36
Table 5.9 Register 8 (Extended ...
Page 37
Reserved Table 5.18 Mode Control/ Status Register 17: Vendor-Specific RSVD EDPWRDOWN RSVD LOWSQEN RSVD = Reserved ...
Page 38
Table 5.23 Symbol Error Counter Register 26: Vendor-Specific Table 5.24 Special Control/Status Indications Register 27: Vendor-Specific AMDIXCTRL ...
Page 39
Reserved Reserved Table 5.28 PHY Special Control/Status Register 31: Vendor-Specific Reserved Autodone Reserved Table 5.26 Interrupt Source Flags Register 29: Vendor-Specific 10 ...
Page 40
SMI Register Mapping The following registers are supported (register numbers are in decimal): REGISTER # 0 Basic Control Register 1 Basic Status Register 2 PHY Identifier 1 3 PHY Identifier 2 4 Auto-Negotiation Advertisement Register 5 Auto-Negotiation Link Partner ...
Page 41
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet ADDRESS NAME 0.15 Reset 1 = software reset. Bit is self-clearing. For best results, 0.14 Loopback 1 = loopback mode normal operation 0.13 Speed ...
Page 42
Table 5.31 Register 1 - Basic Status (continued) ADDRESS NAME 1.4 Remote Fault 1 = remote fault condition detected remote fault 1.3 Auto-Negotiate 1 = able to perform auto-negotiation function 0 = unable to perform auto-negotiation function ...
Page 43
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet Table 5.34 Register 4 - Auto Negotiation Advertisement (continued) ADDRESS NAME 4.9 100Base-T4 4.8 100Base-TX Full Duplex 4.7 100Base-TX 4.6 10Base-T Full Duplex 4.5 10Base-T 4.4:0 ...
Page 44
Table 5.36 Register 6 - Auto Negotiation Expansion ADDRESS NAME 6.15:5 Reserved 6.4 Parallel Detection Fault 6.3 Link Partner Next Page Able 6.2 Next Page Able 6.1 Page Received 6.0 Link Partner Auto- Negotiation Able Table 5.37 Register 16 - ...
Page 45
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet Table 5.38 Register 17 - Mode Control/Status (continued) ADDRESS NAME 17.8:7 Reserved 17.6 ALTINT 17.5:4 Reserved 17.3 PHYADBP 17.2 Force Good Link Status 17.1 ENERGYON 17.0 ...
Page 46
Table 5.41 Register 27 - Special Control/Status Indications ADDRESS NAME 27.15 AMDIXCTRL 27.14 Reserved 27.13 CH_SELECT 27.12 Reserved 27:11 SQEOFF 27.10:5 Reserved 27.4 XPOL 27.3:0 Reserved Table 5.42 Register 28 - Special Internal Testability Controls ADDRESS NAME 28.15:0 Reserved Table ...
Page 47
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet Table 5.43 Register 29 - Interrupt Source Flags (continued) ADDRESS NAME 29.1 INT1 29.0 Reserved ADDRESS NAME 30.15:8 Reserved 30.7:1 Mask Bits 30.0 Reserved Table 5.45 ...
Page 48
Interrupt Management The Management interface supports an interrupt capability that is not a part of the IEEE 802.3 specification. It generates an active low asynchronous interrupt signal on the nINT output whenever certain events are detected as setup by ...
Page 49
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet 5.3.2 Alternate Interrupt System The Alternative method is enabled by writing a ‘1’ to 17.6 (ALTINT). To set an interrupt, set the corresponding bit of the ...
Page 50
Collision Detect A collision is the occurrence of simultaneous transmit and receive operations. The COL output is asserted to indicate that a collision has been detected. COL remains active for the duration of the collision. COL is changed asynchronously ...
Page 51
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet the PHY powers-up. It automatically resets itself into the state it had prior to power-down, and asserts the nINT interrupt if the ENERGYON interrupt is enabled. ...
Page 52
The four LED signals can be either active-high or active-low. Polarity depends upon the Phy address latched in on reset. The LAN8700/LAN8700i senses each Phy address bit and changes the polarity of the LED signal accordingly. If the address bit ...
Page 53
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet data that is received from the link partner on the MDI is looped back out to the link partner. The digital interface signals on the local ...
Page 54
PHY application, this ensures that the scramblers are out of synchronization and disperses the electromagnetic radiation across the frequency spectrum. 5.4.9.2 Mode Bus – MODE[2:0] The MODE[2:0] bus controls the configuration of the 10/100 digital block. When the nRST pin ...
Page 55
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet Chapter 6 AC Electrical Characteristics The timing diagrams and limits in this section define the requirements placed on the external signals of the Phy. 6.1 Serial ...
Page 56
MII 10/100Base-TX/RX Timings 6.2.1 MII 100Base-T TX/RX Timings 6.2.1.1 100M MII Receive Timing Clock Out - RX_CLK T Data Out - RXD[3:0] RX_DV RX_ER Figure 6.2 100M MII Receive Timing Diagram Table 6.2 100M MII Receive Timing Values PARAMETER ...
Page 57
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet 6.2.1.2 100M MII Transmit Timing Clock Out - TX_CLK Data Out - TXD[3:0] TX_EN TX_ER Figure 6.3 100M MII Transmit Timing Diagram Table 6.3 100M MII ...
Page 58
MII 10Base-T TX/RX Timings 6.2.2.1 10M MII Receive Timing Clock Out - RX_CLK Data Out - RXD[3:0] RX_DV Figure 6.4 10M MII Receive Timing Diagram Table 6.4 10M MII Receive Timing Values PARAMETER DESCRIPTION T4.1 Receive signals setup to ...
Page 59
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet 6.2.2.2 10M MII Transmit Timing Clock Out - TX_CLK Data Out - TXD[3:0] TX_EN Figure 6.5 10M MII Transmit Timing Diagrams Table 6.5 10M MII Transmit ...
Page 60
Table 6.6 100M RMII Receive Timing Values PARAMETER DESCRIPTION T6.1 Output delay from rising edge of CLKIN to receive signals output valid CLKIN frequency 6.3.1.2 100M RMII Transmit Timing Clock In - CLKIN Data Out - TXD[1:0] TX_EN Figure 6.7 ...
Page 61
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet 6.3.2 RMII 10Base-T TX/RX Timings 6.3.2.1 10M RMII Receive Timing Clock In - CLKIN Data Out - RXD[1:0] CRS_DV Figure 6.8 10M RMII Receive Timing Diagram ...
Page 62
RMII Transmit Timing Clock In - CLKIN Data Out - TXD[1:0] TX_EN Figure 6.9 10M RMII Transmit Timing Diagram Table 6.9 10M RMII Transmit Timing Values PARAMETER DESCRIPTION T10.1 Transmit signals required setup to rising edge of CLKIN ...
Page 63
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet 6.5 Reset Timing nRST Configuration Signals O utput drive PARAMETER DESCRIPTION T11.1 Reset Pulse Width T11.2 Configuration input setup to nRST rising T11.3 Configuration input hold ...
Page 64
Clock Circuit LAN8700/LAN8700i can accept either a 25MHz crystal or a 25MHz single-ended clock oscillator (±50ppm) input for operation in MII mode. If the single-ended clock oscillator method is implemented, XTAL2 should be left unconnected and XTAL1/CLKIN should be ...
Page 65
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet Chapter 7 DC Electrical Characteristics 7.1 DC Characteristics 7.1.1 Maximum Guaranteed Ratings Stresses beyond those listed in may cause permanent damage to the device. Exposure to ...
Page 66
IEN/IEC61000-4-2 Performance The EN/IEC61000-4-2 ESD specification is an international standard that addresses system-level immunity to ESD strikes while the end equipment is operational. In contrast, the HBM ESD tests are performed at the device level with the device powered ...
Page 67
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet Table 7.4 Power Consumption Device Only POWER PIN GROUP Typical 100BASE-T /W TRAFFIC Typical 10BASE-T /W TRAFFIC ENERGY DETECT POWER Typical DOWN Typical GENERAL POWER DOWN ...
Page 68
DC Characteristics - Input and Output Buffers NAME V IH TXD0 0.68 * VDDIO TXD1 0.68 * VDDIO TXD2 0.68 * VDDIO TXD3 0.68 * VDDIO TX_EN 0.68 * VDDIO TX_CLK RXD0/MODE0 RXD1/MODE1 RXD2/MODE2 RXD3/nINTSEL RX_ER/RXD4 RX_DV RX_CLK/REGOFF CRS/PHYAD4 ...
Page 69
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet NAME TXP TXN See Table 7.12, “100Base-TX Transceiver Characteristics,” on page 71 RXP RXN NAME V IH SPEED100/PHYAD0 0.68 * VDDIO LINK/PHYAD1 0.68 * VDDIO ACTIVITY/PHYAD2 ...
Page 70
NAME nINT/TX_ER/TXD4 nRST 0.68 * VDDIO CLKIN/XTAL1 (Note 7.3) +1.40 V XTAL2 NC Note 7.3 These levels apply when a 0-3.3V Clock is driven into CLKIN/XTAL1 and XTAL2 is floating. The maximum input voltage on XTAL1 is VDDIO + 0.4V. ...
Page 71
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet Note: For VDDIO operation below +2.5V, SMSC recommends designs add external strapping resistors in addition the internal strapping resistors to ensure proper strapped operation. Table 7.12 ...
Page 72
Chapter 8 Application Notes 8.1 Application Diagram VDD3.3 12.4k 1% nINT/TX_ER/TXD4 CRS/PHYAD4 MDIO nRST TX_EN VDD33 VDD_CORE SPEED100/PHYAD0 Speed100 Figure 8.1 Simplified Application Diagram (see Revision 2.2 (12-04-09) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and ...
Page 73
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet Note the Crystal is used to control the crystal drive strength into the PHY clock generator. This resistance can be fine tuned to meet ...
Page 74
Includes Probe Points on All MII Data and Control Signals for Troubleshooting Includes 25MHz Crystal for Internal PHY Reference; RX_CLK is Supplied to the 40-Pin Connector Supports user configuration options including PHY address selection Integrated 3.3V Regulator APPLICATIONS The EVB8700 ...
Page 75
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet Chapter 9 Package Outline, Tape and Reel Figure 9.1 36-Pin QFN Package Outline 0.90 mm Body (Lead-Free) Table 9.1 36-Pin QFN Package ...
Page 76
Revision 2.2 (12-04-09) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Figure 9.2 QFN, 6x6 Tape & Reel 76 DATASHEET ® Technology in a Small Footprint Datasheet SMSC LAN8700/LAN8700i ...
Page 77
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet Note: Standard reel size is 3000 pieces per reel. SMSC LAN8700/LAN8700i ® Technology in a Small Footprint Figure 9.3 Reel Dimensions 77 DATASHEET Revision 2.2 (12-04-09) ...
Page 78
Chapter 10 Revision History REVISION LEVEL & DATE SECTION/FIGURE/ENTRY Rev. 2.2 Table 6.1, "SMI Timing Values" (12-04-09) Rev. 2.1 Section 5.4.6 (03-06-09) Table 5.34 Section 6.3 Section 5.4.8 Section 4.6.3 Section 6.6 Figure 1.1 Section 4.11 Table 5.45 Table 5.28 ...
Page 79
ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR Datasheet Table 10.1 Customer Revision History (continued) REVISION LEVEL & DATE SECTION/FIGURE/ENTRY Rev. 1.8 Table 6.7 (02-14-08) Rev. 1.8 Table 6.6 (02-14-08) Rev. 1.6 Section 4.9 (12-11-07) ...
Page 80
Table 10.1 Customer Revision History (continued) REVISION LEVEL & DATE SECTION/FIGURE/ENTRY Rev. 1.1 Table 5.40 (04-12-07) Rev. 1.1 Table 5.29 (04-12-07) Rev. 1.1 Table 5.23 (04-12-07) Rev. 1.0 Table 5.30, “Register 0 - Basic (04-04-07) Control,” on page 41 Rev ...