LAN9215-MT Standard Microsystems (SMSC), LAN9215-MT Datasheet - Page 14

• Manufacturer Part Number: LAN9215-MT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9215-MT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

Revision 2.7 (03-15-10)
1.12
1.13
The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as
an interface for the LAN9215 Control and Status Registers (CSR’s).
The host bus interface is the primary bus for connection to the embedded host system. This interface
models an asynchronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface.
Programmed I/O transactions are supported.
The LAN9215 host bus interface supports 16-bit bus transfers. Internally, all data paths are 32-bits
wide. The LAN9215 can be interfaced to either Big-Endian or Little-Endian processors.
The LAN9215 also supports the ability to interface to an external PHY device. This interface is
compatible with all IEEE 802.3 MII compliant physical layer devices. For additional information on the
MII interface and associated signals, please refer to
Switching," on page 46
Host Bus Interface (SRAM Interface)
External MII Interface
for more information.
DATASHEET
14
16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support
Section 3.11, "MII Interface - External MII
SMSC LAN9215
Datasheet