LAN9215-MT Standard Microsystems (SMSC), LAN9215-MT Datasheet - Page 117
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LAN9215-MT
Manufacturer Part Number
LAN9215-MT
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9215-MT.pdf
(143 pages)
Specifications of LAN9215-MT
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
2.97V
Operating Supply Voltage (max)
3.63V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Lead Free Status / RoHS Status
Compliant
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16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9215
5.5.9
ADDRESS
15-8
MODE
7:5
4:0
000
001
010
100
101
011
110
111
Special Modes
Note 5.5
Reserved
MODE: PHY Mode of operation. Refer to
PHYAD: PHY Address:
The PHY Address is used for the SMI address.
10Base-T Half Duplex. Auto-negotiation disabled.
10Base-T Full Duplex. Auto-negotiation disabled.
100Base-TX Half Duplex. Auto-negotiation disabled.
CRS is active during Transmit & Receive.
100Base-TX Full Duplex. Auto-negotiation disabled.
CRS is active during Receive.
100ase-TX Half Duplex is advertised. Auto-
negotiation enabled.
CRS is active during Transmit & Receive.
Repeater mode. Auto-negotiation enabled.
100Base-TX Half Duplex is advertised.
CRS is active during Receive.
Reserved - Do not set the LAN9215 in this mode.
All capable. Auto-negotiation enabled.
Index (In Decimal):
When MODE=111, the register 0 bits 13 and 8 are variable dependant on the auto-
negotiated speed and duplex.
MODE DEFINITIONS
Table 5.9 MODE Control
DESCRIPTION
18
DATASHEET
117
Table 5.9
Size:
for more details.
DEFAULT REGISTER BIT VALUES
REGISTER 0
[13,12,10,8]
Note 5.5
X10X
0000
0001
1000
1001
1100
1100
N/A
16-bits
NASR
NASR
NASR
TYPE
RW,
RW,
RW,
REGISTER 4
Revision 2.7 (03-15-10)
[8,7,6,5]
0100
0100
1111
N/A
N/A
N/A
N/A
N/A
DEFAULT
Table 5.9
00001b
See