LAN91C96-MS Standard Microsystems (SMSC), LAN91C96-MS Datasheet - Page 76

• Manufacturer Part Number: LAN91C96-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN91C96-MS

• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

Note:
Revision 1.0 (10-24-08)
1.
2.
The pointer register is shared by any process accessing the LAN91C96 memory. In order to allow
processes to be interruptible, the interrupting process is responsible for reading the pointer value before
modifying it, saving it, and restoring it before returning from the interrupt.
Typically there would be three processes using the pointer:
1)
2)
3)
1) and 3) also share the usage of the Packet Number Register. Therefore saving and restoring the PNR is
also required from interrupt service routines.
POWER DOWN
The LAN91C96 can enter power down mode by means of the PWRDWN pin (pin 68) or the PWRDN bit
(Control Register, bit 13). When in power down mode, the LAN91C96 will:
The PWRDWN pin is internally gated with the RESET (RESET pin before de-glitching) and with the
SRESET bit (COR bit 7). This gating function internally negates power down whenever RESET is high or
SRESET is high to allow the oscillator to run during RESET. Except for this gating function, all other uses
of the RESET pin use a de-glitched version of the signal as defined in the pin description section.
One interrupt per packet: enable TX INT, set AUTO RELEASE=0. The software driver can find the
completion result in memory and process the interrupt one packet at a time. Depending on the
completion code the driver will take different actions. Note that the transmit process is working in
parallel and other transmissions might be taking place. The LAN91C96 is virtually queuing the packet
numbers and their status words.
In this case, the transmit interrupt service routine can find the next packet number to be serviced by
reading the TX FIFO PACKET NUMBER at the FIFO PORTS register. This eliminates the need for
the driver to keep a list of packet numbers being transmitted. The numbers are queued by the
LAN91C96 and provided back to the CPU as their transmission completes.
One interrupt per sequence of packets: Enable TX EMPTY INT and TX INT, set AUTO RELEASE=1.
TX EMPTY INT is generated only after transmitting the last packet in the FIFO. TX INT will be set on
a fatal transmit error allowing the CPU to know that the transmit process has stopped and therefore
the FIFO will not be emptied.
This mode has the advantage of a smaller CPU overhead, and faster memory de-allocation. Note that
when AUTO RELEASE=1 the CPU is not provided with the packet numbers that completed
successfully.
Transmit loading (sometimes interrupt driven)
Receive unloading (interrupt driven)
Transmit Status reading (interrupt driven).
Stop the crystal oscillator
Tristate: Data Bus
Drive the EEPROM and ROM outputs inactive
Preserve contents of registers and memory
−
−
−
−
Interrupts(only by PWRDN bit)
nIOCS16
10BASE-T and AUI outputs
Turn off analog bias currents
DATASHEET
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
SMSC LAN91C96 5v&3v
Datasheet