LAN91C96-MS Standard Microsystems (SMSC), LAN91C96-MS Datasheet - Page 68

• Manufacturer Part Number: LAN91C96-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN91C96-MS

• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

8.2
Revision 1.0 (10-24-08)
7 a)
1 ISSUE ALLOCATE MEMORY FOR TX - N
2 WAIT FOR SUCCESSFUL COMPLETION
3 LOAD TRANSMIT DATA - Copy the TX packet
4 ISSUE "ENQUEUE PACKET NUMBER TO TX
5
6
b)
BYTES - the MMU attempts to allocate N bytes
of RAM.
CODE - Poll until the ALLOC INT bit is set or
enable its mask bit and wait for the interrupt.
The TX packet number is now at the Allocation
Result Register.
number into the Packet Number Register. Write
the Pointer Register, then use a block move
operation from the upper layer transmit queue
into the Data Register.
FIFO" - This command writes the number
present in the Packet Number Register into the
TX FIFO. The transmission is now enqueued.
No further CPU intervention is needed until a
transmit interrupt is generated.
Typical Flow of Events for Transmit (Auto Release = 1)
SERVICE INTERRUPT - Read Interrupt
Status Register. If it is a transmit interrupt,
read the TX FIFO Packet Number from the
FIFO Ports Register. Write the packet
number into the Packet Number Register.
The corresponding status word is now
readable from memory. If status word
shows successful transmission, issue
RELEASE packet number command to free
up the memory used by this packet.
Remove packet number from completion
FIFO by writing TX INT Acknowledge
Register.
Option 1) Release the packet.
Option 2) Check the transmit status in the
EPH STATUS Register, write the packet
number of the current packet to the Packet
Number Register, re-enable TXENA, then
go to step 4 to start the TX sequence again.
S/W DRIVER
DATASHEET
Page 68
The enqueued packet will be transferred to the
MAC block as a function of TXENA (nTCR) bit
and of the deferral process (1/2 duplex mode
only) state.
Transmit pages are released by transmit
completion.
Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
MAC SIDE
SMSC LAN91C96 5v&3v
Datasheet