LAN91C96-MS Standard Microsystems (SMSC), LAN91C96-MS Datasheet - Page 45

• Manufacturer Part Number: LAN91C96-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN91C96-MS

• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
SMSC LAN91C96 5v&3v
AUI
X
X
X
X
1
0
I/O SPACE - BANK0
This register stores the status of the last transmitted frame. This register value, upon individual transmit
packet completion, is stored as the first word in the memory area allocated to the packet. Packet interrupt
processing should use the copy in memory as the register itself will be updated by subsequent packet
transmissions. The register can be used for real time values (like TXENA and LINK OK). If TXENA is
cleared the register holds the last packet completion status.
Reserved – Must be 0.
LINK_OK - State of the 10BASE-T Link Integrity Test. A transition on the value of this bit generates an
interrupt when the LE ENABLE bit in the Control Register is set.
RES – This bit is reserved and will always return a zero(0).
CTR_ROL - Counter Roll over. When set one or more 4 bit counters have reached maximum count (15).
Cleared by reading the ECR register.
EXC_DEF - Excessive deferral. When set last/current transmit was deferred for more than 1518 * 2 byte
times. Cleared at the end of every packet sent.
LOST_CARR - Lost carrier sense. When set indicates that Carrier Sense was not present at end of
preamble. Valid only if MON_CSN is enabled. This condition causes TXENA bit in TCR to be reset.
Cleared by setting TXENA bit in TCR.
LATCOL - Late collision detected on last transmit frame. If set a late collision was detected (later than 64
byte times into the frame). When detected the transmitter JAMs and turns itself off clearing the TXENA bit
in TCR. Cleared by setting TXENA in TCR.
OFFSET
Reserved
2
DEFR
FDSE
TX
0
0
X
X
0
0
0
1
FDUPLX
LINK_
BRD
LTX
OK
0
0
X
1
1
1
0
1
EPH STATUS REGISTER
SQET
RES
EPH_LOOP
0
0
DATASHEET
Table 7.1 - Transmit Loop
NAME
1
0
0
0
0
0
16COL
_ROL
CTR
0
0
Page 45
LOOP
X
1
0
0
0
0
MULT
_DEF
EXC
LTX
0
0
NORMAL CSMA/CD -
10BASE-T Driver
ETHERNET - No
loopback and No
FULL DUPLEX
CARR
LOST
No Loopback
MUL
COL
SWITCHED
LOOPS AT
EPH Block
0
0
ENDEC
SQET
Cable
READ ONLY
TYPE
LATCOL
SNGL
COL
0
0
TO NETWORK
WAKEUP
TX_SUC
TRANSMITS
SYMBOL
EPHSR
0
0
Yes
Yes
Yes
Yes
No
No
Revision 1.0 (10-24-08)