LAN9221I-ABZJ Standard Microsystems (SMSC), LAN9221I-ABZJ Datasheet - Page 151

• Manufacturer Part Number: LAN9221I-ABZJ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9221I-ABZJ

• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (min): 1.62V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
Chapter 9 Revision History
SMSC LAN9221/LAN9221i
REVISION LEVEL & DATE
(03-15-10)
(10-24-08)
(08-18-08)
(06-19-08)
(06-10-08)
(11-13-08)
Rev. 2.7
Rev. 2.5
Rev. 2.4
Rev. 2.3
Rev. 2.2
Rev. 2.2
Chapter 2, "Pin Description
and Configuration," on
page 15
Section 7.2, "Operating
Conditions**," on page 140
Section 6.9, "Power
Sequence Timing," on
page 137
All
All
Table 7.1 on page 141
Table 7.2 on page 142
Section 7.5, "Worst Case
Current Consumption," on
page 143
Section 7.6, "DC Electrical
Specifications," on page 144
Section 3.8, "General
Purpose Timer (GP Timer),"
on page 38
Section 5.3.23, "E2P_CMD
– EEPROM Command
Register," on page 103
Table 7.11 on page 148
Note 7.9 on page 146
Figure 1.2, "Internal Block
Diagram"
Table 2.4, “System and
Power Signals,” on page 18
Auto-negotiation
Advertisement on page 121
SECTION/FIGURE/ENTRY
Table 9.1 Customer Revision History
DATASHEET
and
151
Added pin 1 designator to pin diagram
Added note: “Do not drive input signals without
power supplied to the device.”
Added power sequence timing section
Fixed various typos
Fixed various typos
Added power consumption values.
Updated with current consumption values for
various VDDVARIO values.
Added input capacitance and input leakage values.
Changed incorrect “GPT_CNT” reference to
“GPT_LOAD”: “On a reset, or when the
TIMER_EN bit changes from set ‘1’ to cleared ‘0,’
the GPT_LOAD field is initialized to FFFFh.”
Corrected MAC Address Loaded (bit 8) type from
“RO” to “R/WC”
Updated crystal specifications:
Drive Level: 300uW
ESR: 50 Ohms.
Note following I/O Buffer Characteristics table
modified:
Changed from: ".....the per-pin input leakage is 10
divided by the maximum input leakage current."
to: ".....the per-pin input leakage is the maximum
input leakage current divided by 10."
Diagram redone.
The word “Core” was added to the regulator block
title.
Changed VDD_CORE/VDD18CORE bulk
capacitor value from 10uF to 4.7uF.
Bits 9 and 15 relabeled as Reserved, Read-Only
(RO), with a default of 0.
CORRECTION
Revision 2.7 (03-15-10)