RC82540EP Intel, RC82540EP Datasheet - Page 15

• Manufacturer Part Number: RC82540EP
• Manufacturer: Intel

Specifications of RC82540EP

• Operating Supply Voltage (typ): 1.5/2.5/3.3V
• Operating Supply Voltage (min): 1.43/2.38/3V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Not Compliant

3.2.2
3.2.3
3.2.4
3.2.5
Interrupt Signal
Error Reporting Signals
Arbitration Signals
System Signals
REQ#
GNT#
LOCK#
INTA#
CLK
M66EN
RST#
CLK_RUN#
SERR#
PERR#
Symbol
Symbol
Symbol
Symbol
TS
I
I
TS
I
I
I
I/O
OD
OD
STS
Type
Type
Type
Type
Request Bus. The Request Bus signal is used to request control of the bus from the
arbiter. This signal is point-to-point.
Grant Bus. The Grant Bus signal notifies the 82540EP that bus access has been
granted. This is a point-to-point signal.
Lock Bus. The Lock Bus signal is asserted by an initiator to require sole access to a
target memory device during two or more separate transfers. The 82540EP device
does not implement bus locking.
Interrupt A. Interrupt A is used to request an interrupt by port 1 of the 82540EP. It is an
active low, level-triggered interrupt signal.
PCI Clock. The PCI Clock signal provides timing for all transactions on the PCI bus
and is an input to the 82540EP device. All other PCI signals, except the Interrupt A
(INTA#) and PCI Reset signal (RST#), are sampled on the rising edge of CLK. All other
timing parameters are defined with respect to this edge.
66 MHz Enable. M66EN indicates whether the system bus is enabled for 66 MHz.
PCI Reset. When the PCI Reset signal is asserted, all PCI output signals, except the
Power Management Event signal (PME#), are floated and all input signals are ignored.
The PME# context is preserved, depending on power management settings.
Most of the internal state of the 82540EP is reset on the de-assertion (rising edge) of
RST#.
Clock Run. This signal is used by the system to pause the PCI clock signal. It is used
by the 82540EP controller to request the PCI clock. When the CLK_RUN# feature is
disabled, leave this pin unconnected.
System Error. The System Error signal is used by the 82540EP controller to report
address parity errors. SERR# is open drain and is actively driven for a single PCI clock
when reporting the error.
Parity Error. The Parity Error signal is used by the 82540EP controller to report data
parity errors during all PCI transactions except by a Special Cycle. PERR# is sustained
tri-state and must be driven active by the 82540EP controller two data clocks after a
data parity error is detected. The minimum duration of PERR# is one clock for each
data phase a data parity error is present.
Name and Function
Name and Function
Name and Function
Name and Function
Networking Silicon — 82540EP
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