RC82540EP Intel, RC82540EP Datasheet - Page 13

• Manufacturer Part Number: RC82540EP
• Manufacturer: Intel

Specifications of RC82540EP

• Operating Supply Voltage (typ): 1.5/2.5/3.3V
• Operating Supply Voltage (min): 1.43/2.38/3V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Not Compliant

3.0
3.1
3.2
3.2.1
Note: The targeted signal names are subject to change without notice. Verify with your local Intel sales
Signal Type Definitions
PCI Bus Interface
Signal Descriptions
office that you have the latest information before finalizing a design.
The signals of the 82540EP controller are electrically defined as follows:
When the Reset signal (RST#) is asserted, the 82540EP will not drive any PCI output or bi-
directional pins except the Power Management Event signal (PME#).
PCI Address, Data and Control Signals
I
O
TS
STS
OD
A
P
AD[31:0]
Symbol
Name
Input. Standard input only digital signal.
Output. Standard output only digital signal.
Tri-state. Bi-directional three-state digital input/output signal.
Sustained Tri-state. Sustained digital three-state signal driven by one agent at a time.
An agent driving the STS pin low must actively drive it high for at least one clock before letting it
float. The next agent of the signal cannot drive the pin earlier than one clock after it has been
released by the previous agent.
Open Drain. Wired-OR with other agents.
The signaling agent asserts the OD signal, but the signal is returned to the inactive state by a
weak pull-up resistor. The pull-up resistor may require two or three clock periods to fully restore
the signal to the de-asserted state.
Analog. PHY analog data signal.
Power. Power connection, voltage reference, or other reference connection.
TS
Type
Address and Data. Address and data signals are multiplexed on the same PCI pins. A
bus transaction includes an address phase followed by one or more data phases.
The address phase is the clock cycle when the Frame signal (FRAME#) is asserted
low. During the address phase AD[31:0] contain a physical address (32 bits). For I/O,
this is a byte address, and for configuration and memory, a DWORD address. The
82540EP device uses little endian byte ordering.
During data phases, AD[7:0] contain the least significant byte (LSB) and AD[31:24]
contain the most significant byte (MSB).
Name and Function
Definition
Networking Silicon — 82540EP
7