RU82566DM S L95J Intel, RU82566DM S L95J Datasheet - Page 5

• Manufacturer Part Number: RU82566DM S L95J
• Manufacturer: Intel

Specifications of RU82566DM S L95J

• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 81
• Lead Free Status / RoHS Status: Compliant

ICH9/82566/82567LM/82567V—NVM Information Guide
1.0
1.1
1.2
Non-Volatile Memory (NVM)
Introduction
The document is intended for designs using a 10/100/1000 Mb/s Media Access
Controller (MAC) that is integrated into an Intel
conjunction with an 82566/82567LM/82562V Physical Layer Transceiver (PHY).
The NVM space is used for hardware and software configuration. It is also read by
software to determine and configure specific design features.
Unless otherwise specified, all numbers in this document use the following numbering
convention:
NVM Programming Procedure Overview
The LAN NVM shares space on an SPI Flash device (or devices) along with the BIOS,
Manageability Firmware, and a Flash Descriptor Region. It is programmed through the
ICH9. This combined image is shown in
define vendor specific information and the location, allocated space, and read and write
permissions for each region. The Manageability (ME) Region contains the code and
configuration data for ME functions such as Intel
and Advanced Fan Speed Control. The system BIOS is contained in the BIOS Region.
The ME Region and BIOS Region are beyond the scope of this document and a more
detailed explanation of these areas can be found in the Intel
(ICH9) Family External Design Specification (ICH9 EDS). This document describes the
LAN image contained in the Gigabit Ethernet (GbE) region. Fast Ethernet (82562V)
images are also described.
• Numbers that do not have a suffix are decimal (base 10).
• Numbers with a suffix of “h” are hexadecimal (base 16).
• Numbers with a suffix of “b” are binary (base 2).
Figure
1. The Flash Descriptor Region is used to
®
®
I/O Control Hub 9 (ICH9) device in
Active Management Technology, ASF,
®
I/O Controller Hub 9
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