RU82566DM S L95J Intel, RU82566DM S L95J Datasheet - Page 15

• Manufacturer Part Number: RU82566DM S L95J
• Manufacturer: Intel

Specifications of RU82566DM S L95J

• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 81
• Lead Free Status / RoHS Status: Compliant

ICH9/82566/82567LM/82567V—NVM Information Guide
1.4.17
Table 13.
1.4.18
Table 14.
1.4.19
Table 15.
Extended Configuration Word 2 (Word 15h)
1. 82566 only.
Extended Configuration Word 3 (Word 16h)
LED 1 Configuration and Power Management (Word 17h)
This field specifies the default values for the LEDCTL register fields controlling the LED1
(LINK_1000) output behaviors and the OEM fields defining the PHY power management
parameters loaded to the PHY_CTRL register.
LED 1 Configuration and Power Management (Word 17h)
Extended Configuration Word 2 (Word 15h)
Extended Configuration Word 3 (Word 16h)
15:8
7:0
15:0
15
14
13:12
11
10
9
8
Bit
Bit
Bit
Extended
PHY Length
Reserved
Reserved
B2B Enable
GbE Disable
Reserved
GbE Disable in non-
D0a
LPLU Enable in non-
D0a
LPLU Enable
SPD Enable
Name
Name
Name
00h
00h
00111011
Default
00h
1b
0b
0b
00b
1b
0b
1b
0b
0b
1b
0b
Default
Default
1
1
1
1
1
This field identifies the size (in Dwords) of the extended PHY
configuration area.
For the 82566 PHY, if the extended PHY configuration area is
disabled, the length must be set to 00h.
These bits are reserved and should be set to 00h.
These bits are reserved and should be set to 00h.
This bit enables Smart Power Down in back-to-back link setup.
0b = B2B disabled.
1b = B2B enabled.
When this bit is set, GbE operation is disabled in all power states
(including D0a).
0b = GbE enabled.
1b = GbE disabled.
These bits are reserved and should be set to 000b.
This bit disables GbE operation in non-D0a states. This bit must be
set since GbE is not supported in Sx mode by the platform.
0b = GbE enabled.
1b = GbE disabled.
The Low Power Link Up enables link at the lowest speed supported
by both link partners in non-D0a states. This bit must be set if
LPLU Enable bit is set.
0b = Low Power Link Up is disabled.
1b = Low Power Link Up is enabled in all non-D0a states.
The Low Power Link Up enables link at the lowest speed supported
by both link partners in all power states. This bit enables a
decrease in link speed in all power states.
0b = Low Power Link Up is disabled.
1b = Low Power Link Up is enabled in all power states.
0b = PHY Smart Power Down mode is disabled.
1b = PHY Smart Power Down mode is enabled.
Description
Description
Description
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