RU82566DM S L95J Intel, RU82566DM S L95J Datasheet - Page 16

• Manufacturer Part Number: RU82566DM S L95J
• Manufacturer: Intel

Specifications of RU82566DM S L95J

• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 81
• Lead Free Status / RoHS Status: Compliant

Table 15.
Table 16.
16
LED 1 Configuration and Power Management (Word 17h)
1. 82562V only.
The following table lists the LED modes defined in bits 3:0 of this word.
LED Modes
7
6
5
4
3:0
Bit
Mode (Bits
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
3:0)
LED1 Blink
LED1 Invert
LED1 Blink Mode
Activity Mode
Source
LED1 Mode
Name
FILTER_ACTIVITY
Selected Mode
LINK_100/1000
LINK/ACTIVITY
LINK_10/1000
FULL_DUPLEX
LINK_1000
COLLISION
BUS_SIZE
LINK_100
ACTIVITY
Reserved
LED_OFF
LINK_10
LINK-UP
LED_ON
PAUSED
0b
0b
0b
0b
0111b
Default
This bit indicates the initial value of the LED1_BLINK field.
0b = LED1 is non-blinking (recommended).
1b = LED1 is blinking.
This bit indicates the initial value of the LED1_IVRT field.
0b = LED1 has an active low output.
1b = LED1 has an active high output.
This bit defines the LED1 blink mode:
0b = Slow rate.
1b = Fast rate.
This field should be identical to LED0 Blink Mode.
Activity Mode Source (all LEDs) when operating with the 82562V.
When set to 0b, the activity LED is activated by the PHY.
When set to 1b, the activity LED is driven by Tx activity or Rx
traffic that match any of the ICH9's MAC addresses.
0b = PHY indication.
1b = Filter indication.
These bits represent the initial value of the LED1_MODE field,
which specifies the event, state, or pattern displayed on LED1
(LINK_1000) output.
A value of 0111b indicates that a 1000 Mb/s link is established and
maintained.
Asserted when either 10 Mb/s or 1000 Mb/s link is established
and maintained.
Asserted when either 100 Mb/s or 1000 Mb/s link is
established and maintained.
Asserted when any speed link is established and maintained.
Asserted when link is established and packets are being
transmitted or received that passed MAC filtering.
Asserted when link is established and when there is no
transmit or receive activity.
Asserted when a 10 Mb/s link is established and maintained.
Asserted when a 100 Mb/s link is established and maintained.
Asserted when a 1000 Mb/s link is established and maintained.
Reserved.
Asserted when the link is configured for full duplex operation.
Asserted when a collision is observed.
Asserted when link is established and packets are being
transmitted or received.
Asserted when the MAC detects a 1-lane PCIe* connection.
Asserted when the MAC transmitter is flow controlled.
Always asserted.
Always de-asserted.
NVM Information Guide—ICH9/82566/82567LM/82567V
Table 16
Source Indication
Description
defines the values for LED1 Mode.