GD82541PI Intel, GD82541PI Datasheet - Page 10

• Manufacturer Part Number: GD82541PI
• Manufacturer: Intel

Specifications of GD82541PI

• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Not Compliant

82541(PI/GI/EI) — Networking Silicon
2.2
2.3
2.4
12
Figure 2. Internal Architecture Block Diagram
Internal MAC Architecture Block Diagram
Figure 2 shows the major internal function blocks of 82541(PI/GI/EI) MAC device. Compared to
its predecessors, the 82541(PI/GI/EI) MAC adds improved receive-packet filtering to support
SMBus-based manageability, as well as the ability to support transmit of SMBus-based
manageability packets. In addition, an ASF-compliant TCO controller is integrated into the MAC
for reduced-cost basic ASF manageability.
Integrated 10/100/1000Mbps PHY
The 82541(PI/GI/EI) contains an integrated 10/100/1000Mbps-capable Copper PHY. This PHY
communicates with the MAC controller using a standard GMII/MII interface internal to the
component to transfer transmit and receive data. A standard MDIO interface, accessible to
software via MAC control registers, is used to configure and monitor the PHY operation.
System Interface
82541(PI/GI/EI) provides a 32-bit PCI 2.2 bus interface which is capable of up to 66 MHz
operation in conventional PCI mode. In conventional PCI systems with a dedicated I/O bus per
connector, this interface should provide sufficient bandwidth to support a sustained 1000 Mb/sec
transfer rate. 64 KB of on-chip buffering mitigates instantaneous receive bandwidth demands and
eliminates transmit under-runs by buffering the entire outgoing packet prior to transmission.
PCI Interface
EEPROM
PCI/PCI-
X Core
Flash
Host Arbiter
Engine
Packet
Buffer
DMA
Manageability
ASF
SM Bus
Manageability
Packet/
Filter
Switch
TX
1000 Mb)
1000 Mb)
Statistics
TX MAC
RX MAC
(10/100/
(10/100/
RMON
GMII/
MDIO
MII
MDIO
Link I/F