DJLXT380LE.B4 Cortina Systems Inc, DJLXT380LE.B4 Datasheet - Page 21

• Manufacturer Part Number: DJLXT380LE.B4
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT380LE.B4

• Lead Free Status / RoHS Status: Not Compliant

2.0
2.1
2.1.1
2.2
Datasheet
Functional Description
Figure 4 on page 10
interface unit designed for G.703 2.048 Mbps applications.
Each transceiver front end interfaces with four lines, one pair for transmit, one pair for receive.
These two lines comprise a digital data loop for full duplex transmission.
The LXT380 can be controlled through hard-wired pins (Hardware mode) or by a microprocessor
through a serial or parallel interface (Host mode).
The transmitter timing reference is TCLK, and the receiver reference clock is MCLK. The LXT380
is designed to operate without any reference clock when used as an analog front-end (line driver
and data recovery). MCLK is mandatory if the on chip clock recovery capability is used. All eight
clock recovery circuits share the same reference clock defined by the MCLK input signal.
Initialization
During power up, the transceiver remains static until the power supply reaches approximately 60%
of VCC. During power-up, an internal reset sets all registers to 0 and resets the status and state
machines for the LOS.
Reset Operation
Reading or writing the reset register (RES) initiates a 1 microsecond reset cycle. This operation
sets all LXT380 registers to their default values.
Receiver
The eight receivers in the LXT380 are identical. The following paragraphs describe the operation
of a single receiver.
The receive signal is input to the LIU via a 1:1 transformer. A peak detector samples the received
signal and determines its maximum value. A percentage of the peak value is provided to the data
slicers to ensure optimum signal-to-noise ratio.
The receiver is capable of accurately recovering signals with up to 12dB of attenuation (from 2.37
V nominal), corresponding to a received signal level of approximately 500 mV. Regardless of
received signal level, the peak detectors are held above a minimum level of 150 mV to provide
immunity from impulsive noise.
After processing through the data slicers, the received signal is routed to the data ports, the timing
recovery section, and to the receive monitor. The timing recovery circuit provides an input jitter
tolerance significantly better than required by G.823 as shown in
Recovered data is active High and output at RPOS and RNEG, The recovered clock is output at
RCLK. RPOS/RNEG validation is pin selectable (CLKE).
is a block diagram of the LXT380. The LXT380 is a fully integrated octal line
Octal E1 G.703 Transceiver — LXT380
Figure 31 on page
65.
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