DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 53

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

6.1.1
6.1.1.1
6.1.1.2
6.1.1.3
Datasheet
Instruction Register and Definitions
The LXT6282 supports the following instructions IEEE1149.1: EXTEST, SAMPLE/PRELOAD,
BYPASS and IDCODE. Instructions are shifted into the instruction register during the SHIFT-IR
state and become active upon exiting the UPDATE-IR state. The instruction register definition is
shown in the following figure.
EXTEST (‘b00)
This instruction allows the testing of circuitry external to the package, typically the board
interconnect, to be tested. While the instruction is active, the boundary scan register is connected
between TDI and TDO for any data shifts. Boundary scan cells at the output pins are used to apply
test stimuli, while those at input pins capture test results. Signals present on input pins are loaded
into the BSR inputs cells on the rising edge of JTCK during CAPTURE-DR state. BSR contains are
shifted one bit location on each rising edge of JTCK during the SHIFT-DR state. BSR output cell
contents appear at output pins on the falling edge of JTCK during the UPDATE-IR state.
One test cycle is:
SAMPLE/PRELOAD (‘b01)
This instruction allows a snapshot of the normal operation of the LXT6282. The boundary scan
register is connected between the TDI and TDO for any data shifts while this instruction is active.
All BSR cells capture data present at their inputs on the rising edge of JTCK during the
CAPTURE-DR state. No action is taken during the UPDATE-DR state.
BYPASS (‘b11)
This instruction allows a device to be effectively removed from the scan chain by inserting a one-
bit shift register stage between TDI and TDO during data shifts. When the instruction is active, the
test logic has no impact upon the system logic performing its system function. When selected, the
shift-register is set to a logic zero on the rising edge of the JTCK during the CAPTURE-DR state.
1. A test stimuli pattern is shifted into the BSR during SHIFT-DR state
2. This pattern is applied to output pins during the UPDATE-DR state
3. The response is loaded into input BSR cells during the CAPTURE-DR state
4. The results are shifted out and next test stimuli shifted in to the BSR
TDI
MSB
LSB
TDO
LXT6282
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