DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 28

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

LXT6282
3.1.12.3
3.1.12.4
3.1.12.5
28
Interrupt Clearing
In the discussion below it is assumed that the example interrupt sources have their interrupt enable
bits SET.
Status change interrupt sources have their interrupt bits cleared when their status is read. For
example, say the OofSt bit changes from zero to one (in frame to out of frame). Its interrupt bit is
SET by this event. When the microprocessor reads the register containing the OofSt bit its interrupt
bit will be CLEARED. If the OofSt bit subsequently changes from one to zero (out of frame to in
frame) again its interrupt bit is SET by this event and then CLEARED when the status is read.
The interrupt register can be read again only after three interval clock cycles (1.47) have completed
since it has been cleared (by reading its associated status registers).
It should be noted that updates to status bits are not affected by the interrupt bit state. For example,
the OofSt bit could change from a one to zero (generating an interrupt) and then before the
microprocessor reads OofSt it could change back to one. This would have no affect on its interrupt
bit since it would already be SET. When the microprocessor reads the OofSt bit it would read a
one.
Both event interrupts and counter overflow interrupts are cleared when the interrupt register
containing these bits is read (since event and counters do not have any associated status registers).
Status Registers Access
Due to the asynchronous nature of the microprocessor interface and timing differences during
interrupt bit updates, it is possible that a status bit change can fail to SET its associated interrupt bit
if the AlmUpdDsbl bit is not SET during a read of the status registers by the microprocessor. This
situation is very difficult to achieve however, it can happen.
For this reason we encourage programmers to SET the AlmUpdDsbl bit before accessing the status
registers during alarm processing. This effectively locks out internal processes that wish to access
the status and interrupt bits during the time that the microprocessor is accessing these bits. After the
microprocessor is done accessing the status registers it should CLEAR the AlmUpdDsbl bit so that
internal processes may again update the status and interrupt bits.
Counter Reading
Counters are read by first buffering their contents and then reading the buffer. They can be
individually buffered or group buffered. They are group buffered by writing to register BfrAllCntrs
(5FH). They are individually buffered by writing to the most significant byte of a particular buffer.
After buffering the counter, the contents of the buffer are read at the address specified in the
register definition.
For example, to read the contents of the transmitter #1 FrameWord counter a write to register 07H
will buffer only the contents of transmitter #1’s frame word counter. A read of registers 06H and
07H will give the counter value. Alternatively, all of the frame word counters for all 8 transmitters
and receivers can be buffered by writing a 02H to register 5FH.
A counter can be read only after three interval clock cycles (1.47) have completed since it has been
buffered (previous write operation. (JCC)
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