DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 49

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
A<7:0> setup time to read cycle end
A<7:0> hold time from inactive read
A<7:0> setup time to latch
A<7:0> hold time from latch
Valid latch pulse width
AS rising edge to read cycle end setup
RWB setup to active read
RWB hold from inactive read
CSB setup to active read
CSB hold from inactive read
DATA<7:0> access time from valid address
(or ASB whichever comes last for muxed AD bus)
DATA<7:0> bus driven from active read
1. For non-multiplexed Address and Data bus (
2. For multiplexed Address and Data bus (
3. T is the minimum cycle time of either DTCi, either, DRETCKREF, or MTCi (typically 488 ns for E1)
A<7:0>
ASB
CSB
RDB
INT
DATA<7:0>
Figure 10. Microprocessor Read Timing
Table 11. Microprocessor Data Read Timing Parameters
MicroProcessor Read Timing (Intel Mode)
(considering outputs with a 50pF load)
t
SALR
t
Parameter
VL
t
SLR
t
t
t
t
DDR
ADR
AAC
AAC
t
SAR
t
SCR
t
HALR
t
VRD
ASB
t
t
ASB
HAR
INTH
t
HCR
t
used as address latch enable)
HDR
t
ZDR
tied high)
Symbol
t
t
t
t
t
HALR
SALR
t
SRWB
HRWB
t
HAR
SLR
t
t
t
t
t
SAR
VL
SCR
HCR
AAC
DDR
A<7:0>
ASB
RWB
CS
E
INT
DATA<7:0>
2
1
2
2
2
MicroProcessor Read Timing (Motorola Mode)
Min
5
1
4
2
5
6
1
1
1
1
5
t
SALR
t
VL
t
SCR
Typ
t
SRWB
t
t
DDR
ADR
t
t
AAC
AAC
t
t
SLR
SAR
t
HALR
t
VRD
Max
20
t
HRWB
t
t
INTH
HAR
t
HCR
t
HDR
LXT6282
t
ZDR
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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