TTSV04622V2-DB LSI, TTSV04622V2-DB Datasheet - Page 5

• Manufacturer Part Number: TTSV04622V2-DB
• Manufacturer: LSI

Specifications of TTSV04622V2-DB

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

TDCS4810G SONET/SDH
Advance Data Sheet
May 2001
10 Gbits/s APS Port and TSI
List of Tables
(continued)
Contents
Page
Table 52. Audit Memory [23:0] (RO)....................................................................................................................... 65
Table 53. S1 Generation Status (RO) .................................................................................................................... 65
Table 54. S1 Generation Force Toggle (R/W)........................................................................................................ 65
Table 55. Channel Alarm Register (W1C) .............................................................................................................. 66
Table 56. Channel Alarm Mask Register (R/W) ..................................................................................................... 66
Table 57. Path Status (E1/F1) Change Alarm (W1C)............................................................................................. 66
Table 58. Path Status (E1/F1) Change Alarm Mask (R/W) .................................................................................... 67
Table 59. Channel Provisioning Register (R/W) ..................................................................................................... 67
Table 60. Channel Control Register (R/W)............................................................................................................. 68
Table 61. APS Control Register (R/W) ................................................................................................................... 68
Table 62. APS Status Register (RO) ...................................................................................................................... 68
Table 63. APS Insert Value Register (R/W) ........................................................................................................... 68
Table 64. Channel Path Switch Control (R/W) ....................................................................................................... 69
Table 65. Channel Path Switch Readback (RO) .................................................................................................... 69
Table 66. Channel AIS-P Insert (R/W) ................................................................................................................... 69
Table 67. Channel UNEQ-P Insert (R/W)............................................................................................................... 69
Table 68. Extracted Line Status (E2) (RO)............................................................................................................. 69
Table 69. Line Error Counts (RO)........................................................................................................................... 69
Table 70. Channel Alarm Freeze Register (RO) .................................................................................................... 70
Table 71. Connection Memory AC (R/W) ............................................................................................................... 70
Table 72. Connection Memory AD (R/W) ............................................................................................................... 71
Table 73. Connection Memory BC (R/W) ............................................................................................................... 71
Table 74. Connection Memory BD (R/W) ............................................................................................................... 71
Table 75. Extracted Path Status (RO) .................................................................................................................... 71
Table 76. Absolute Maximum Ratings.................................................................................................................... 72
Table 77. ESD Threshold Voltage .......................................................................................................................... 72
Table 78. Recommended Operating Conditions .................................................................................................... 72
Table 79. LVDS Driver dc Data .............................................................................................................................. 75
Table 80. LVDS Driver ac Data .............................................................................................................................. 75
Table 81. LVDS Driver Reference Data ................................................................................................................. 76
Table 82. LVDS Receiver Data .............................................................................................................................. 76
Table 83. LVTTL 3.3 V Logic Interface Characteristics .......................................................................................... 76
Table 84. Microprocessor Interface Timing ............................................................................................................ 77
Table 85. TA_N/TEA_N Cycle Termination for Synchronous Write Cycle ............................................................. 78
Table 86. TA_N/TEA_N Cycle Termination for Synchronous Read Cycle ............................................................. 79
Table 87. TA_N/TEA_N Cycle Termination for Asynchronous Write Cycle ........................................................... 80
Table 88. TA_N/TEA_N Cycle Termination for Asynchronous Read Cycle ........................................................... 81
Table 89. Basic 792-Pin LBGA............................................................................................................................... 84
Agere Systems Inc.
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