TTSV04622V2-DB LSI, TTSV04622V2-DB Datasheet - Page 3

• Manufacturer Part Number: TTSV04622V2-DB
• Manufacturer: LSI

Specifications of TTSV04622V2-DB

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

TDCS4810G SONET/SDH
Advance Data Sheet
May 2001
10 Gbits/s APS Port and TSI
List of Figures
Contents
Page
Figure 1. TDCS4810G Block Diagram ..................................................................................................................... 6
Figure 2. Pin Diagram of 792 LBGA (Bottom View) ................................................................................................. 8
Figure 3. Suggested Schematic for 1.0 V and 1.4 V Reference Voltages .............................................................. 25
Figure 4. Transmitter TOH on LVDS Output .......................................................................................................... 38
Figure 5. SYS_FP Timing Requirements ............................................................................................................... 38
Figure 6. Receiver Block Diagram.......................................................................................................................... 42
Figure 7. Framer State Machine............................................................................................................................. 43
Figure 8. TSHIM Timeline....................................................................................................................................... 45
Figure 9. Connection Memory Physical Organization ............................................................................................ 46
Figure 10. Connection Memory Entry..................................................................................................................... 47
Figure 11. APS Byte Handling................................................................................................................................ 48
Figure 12. APS Byte Switching Example................................................................................................................ 48
Figure 13. Transmitter Block Diagram.................................................................................................................... 51
Figure 14. STS-12 Frame Structure ....................................................................................................................... 52
Figure 15. Illegal Back-to-Back Cross Connect Illustration .................................................................................... 53
Figure 16. Alternate Illegal Back-to-Back Cross Connect Illustration ..................................................................... 53
Figure 17. LVDS Driver and Receiver and Associated Internal Components ........................................................ 74
Figure 18. LVDS Driver and Receiver .................................................................................................................... 74
Figure 19. LVDS Driver .......................................................................................................................................... 74
Figure 20. M860 Synchronous Write Cycle (MPMODE = 10 or 11) ....................................................................... 78
Figure 21. M860 Synchronous Read Cycle (MPMODE = 10 or 11) ....................................................................... 79
Figure 22. M360 Asynchronous Write Cycle (MPMODE = 00)............................................................................... 80
Figure 23. M360 Asynchronous Read Cycle (MPMODE = 00) .............................................................................. 81
Figure 24. DSP R/W Synchronous Write Cycle (MPMODE = 01)—Two or More Wait-States Mode..................... 82
Agere Systems Inc.
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