TTSV04622V2-DB LSI, TTSV04622V2-DB Datasheet - Page 37

• Manufacturer Part Number: TTSV04622V2-DB
• Manufacturer: LSI

Specifications of TTSV04622V2-DB

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

May 2001
Overview
Cross Connect
next A1/A2 boundary; the switch is made during the S1
byte time. The trigger for a switch is configurable on a
per-channel basis. The possible triggers are the follow-
ing:
I
I
I
I
APS Byte Handling
The K1 and K2 bytes of the STS-1 of each channel are
monitored for a change. If a change is detected, a
latched alarm is raised. The received value is stored
and is available in a status register. The LTE is respon-
sible for validating the K bytes and ensuring only the
validated value is sent on the STS-1 of the channel.
Agere LTE chips support this function.
The APS bytes (K1, K2) along with the data communi-
cation bytes (D1—D12) and the line status (E2) can
optionally be switched separately, regardless of the
content of the connection memory. Each output chan-
nel can source these bytes (for all STS-1s in the chan-
nel) from any input channel, bypassing the maps
programmed into the connection memories. This
allows these bytes to take a different path through a
system than the data, easing APS operations in a sys-
tem with multiple cross connects.
Note: When changing the source of these bytes via a
The K1 and K2 bytes of the outgoing channels can be
overridden with a software-programmable value (pro-
grammed on a per-channel basis). The software-pro-
grammed values are inserted in the second time slot
(STS-1 #4) of the output channel, allowing the vali-
dated bytes to pass through from the input to make
them available to subsequent equipment. To use the
inserted values for APS, the LTE must be able to insert
the K1 and K2 from the second time slot into the cor-
rect APS byte positions on the output line. Agere LTE
chips support this function.
Agere Systems Inc.
The SYNC_N pin.
A chip-level control bit.
The S1 byte received in the channel has changed to
or from the value 0xF0.
The S1 byte received in a particular channel
(selected at the top level) has changed to or from the
value 0xF0.
register write, the change occurs immediately
and is not synchronized to the frame boundary.
(continued)
(continued)
E1/F1/E2 Extraction
The E1 and F1 bytes of each STS-1 carry information
indicating the path status of that STS-1. Both bytes
contain the same information. This information can be
used by software to initiate a switch from working to
protected configurations. The E1 and F1 bytes are
extracted from STS-1s at the output of the TSI and
stored.
The bytes are monitored for a change and, if a change
is detected, latched alarms (E1F1ALM, E2ALM) are set
(see Register Descriptions, page 66 and page 62
respectively).
The received values can be read through the micropro-
cessor interface. A single read will return both the E1
and F1 value for a particular STS-1.
The E2 byte of the STS-1 of each STS-12 (channel)
carries information indicating the line status of that
STS-12. This information can be used by software to
initiate a switch from working to protected configura-
tions.
AIS/UNEQ Insertion
Path AIS and UNEQ indications can be inserted on any
STS-1 under software control. This ensures that down-
stream path processors will detect a normal pointer
and will thus be able to extract the path overhead in
order to detect an UNEQ defect. AIS/UNEQ insertion
does not affect E1/F1 or E2 values (or any of the TOH).
AIS insertion takes precedence over UNEQ insertion.
Changes to the AIS/UNEQ microprocessor registers
will not take effect until the next frame boundary.
10 Gbits/s APS Port and TSI
37