LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 436

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LAN9312-NZW

Manufacturer Part Number
LAN9312-NZW
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet

Specifications of LAN9312-NZW

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LAN9312-NZW
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Revision 1.7 (06-29-10)
14.5.4.26
BITS
31:1
0
RESERVED
Interrupt Mask
When set, this bit masks interrupts from the Buffer Manager. The status bits
in the
Buffer Manager Interrupt Mask Register (BM_IMR)
This register contains the Buffer Manager interrupt mask, which masks the interrupts in the
Manager Interrupt Pending Register
the Interrupt Mask bit. Clearing this bit will unmask the interrupts. Refer to
Interrupts," on page 49
Buffer Manager Interrupt Pending Register (BM_IPR)
Register #:
for more information.
1C20h
DESCRIPTION
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
DATASHEET
(BM_IPR). All Buffer Manager interrupts are masked by setting
436
Size:
are not affected.
32 bits
TYPE
R/W
RO
Chapter 5, "System
SMSC LAN9312
DEFAULT
Datasheet
1b
-
Buffer

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