LAN9312-NZW Standard Microsystems (SMSC), LAN9312-NZW Datasheet - Page 260
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LAN9312-NZW
Manufacturer Part Number
LAN9312-NZW
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9312-NZW.pdf
(458 pages)
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Revision 1.7 (06-29-10)
14.2.9.2
BITS
31:0
Byte Test (BYTE_TEST)
This field reflects the current byte ordering
Byte Order Test Register (BYTE_TEST)
This read-only register can be used to determine the byte ordering of the current configuration. Byte
ordering is a function of the host data bus width and endianess. Refer to
on page 99
Note: This register can be read while the LAN9312 is in the reset or not ready states.
The BYTE_TEST register can optionally be used as a dummy read register when assuring minimum
write-to-read or read-to-read timing. Refer to
Write-Read Cycles," on page 101
Cycles," on page 105
Offset:
for additional information on byte ordering.
for additional information.
064h
DESCRIPTION
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
DATASHEET
and
Section 8.4.3, "Special Restrictions on Back-to-Back Read
260
Section 8.4.2, "Special Restrictions on Back-to Back
Size:
32 bits
Section 8.3, "Host Endianess,"
TYPE
RO
SMSC LAN9312
DEFAULT
87654321h
Datasheet
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